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高级ASIC芯片综合——使用Synopsys Design Compiler Physical Compiler和PrimeTime(第2版) 英文原版
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ADVANCED ASIC CHIP SYNTHESIS
Using Synopsys® Design Compiler™
Physical Compiler™ and PrimeTime®
SECON
D
EDITION
Trademark Information
UNIX is a registered trademark of UNIX Systems Laboratories, Inc.
Verilo
g
is a registered trademark of Cadence Design Systems, Inc.
RSPF and DSPF is a trademark of Cadence Design Systems, Inc.
SDF and SPEF is a trademark of Open Verilog International.
Synopsys, PrimeTime, Formality, DesignPower, DesignWare and SOLV-IT! are
registered trademarks of Synopsys, Inc.
Design Analyzer, Design Vision, Physical Compiler, Design Compiler, DFT
Compiler, VHDL Compiler, HDL Compiler, ECO Compiler, Library Compiler,
Synthetic Libraries, DesignTime, Floorplan Manager, characterize, dont_touch,
dont_touch_network and uniquify, are trademarks of Synopsys, Inc.
SolvNET is a service mark of Synopsys, Inc.
All other brand or product names mentioned in this document, are trademarks or
registered trademarks of their respective companies or organizations.
All ideas and concepts provided in this book are authors own, and are not endorsed
by Synopsys, Inc. Synopsys, Inc. is not responsible for information provided in this
book.
ADVANCED ASIC
CHIP SYNTHESIS
Using Synopsys® Design Compiler™
Physical Compiler™ and PrimeTime®
SECOND EDITION
Himanshu Bhatnagar
Conexant Systems, Inc.
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: 0-306-47507-3
Print ISBN: 0-7923-7644-7
©2002 Kluwer Academic Publishers
New York, Boston, Dordrecht, London, Moscow
Print ©2002 Kluwer Academic Publishers
All rights reserved
No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Kluwer Online at: http://kluweronline.com
and Kluwer's eBookstore at: http://ebooks.kluweronline.com
Dordrecht
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