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最近一直在学习pcie,找到了这个资料,大家一起来学习吧! PEX_8619BA_BB_RDK_HRM_15Apr09.pdf (1.73 MB, 下载次数: 75 ) PCIE , PLX , switch
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PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2009 by PLX Technology, Inc. All rights reserved 2
© 2009 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor
variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Document Number: PEX8619BA-Base Board RDK-HRM-1.0
April 15, 2009
![](https://csdnimg.cn/release/download_crawler_static/11712507/bg3.jpg)
PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2009 by PLX Technology, Inc. All rights reserved i
PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may not be
copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to entirely
verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured
products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this
information. The information in this document is subject to change without notice. Although every effort has been
made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential
damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes
no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which
may arise through the use of the RDK, or for any damage or loss caused by deletion of data as a result of
malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PEX 8619BA-Base Board RDK, a Rapid Development Kit, from a hardware
perspective. It contains a description of all major functional circuit blocks on the board and also is a reference for
the creation of software for this product. This manual also includes complete schematics and bill of materials.
REVISION HISTORY
Date Version Comments
April 2009 1.0 Initial Release
![](https://csdnimg.cn/release/download_crawler_static/11712507/bg4.jpg)
PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2009 by PLX Technology, Inc. All rights reserved ii
CONTENTS
NOTICE ......................................................................................................................................................................... i
ABOUT THIS MANUAL ..................................................................................................................................................... i
REVISION HISTORY .................................................................................................................................................... i
1. General Information ........................................................................................................................................... 1
1.1 PEX 8619 Features ................................................................................................................................... 1
1.2 PEX 8619BA-BB RDK Features ................................................................................................................ 3
2. System Architecture ........................................................................................................................................... 4
3. Hardware Architecture ....................................................................................................................................... 5
3.1 PEX 8619 ................................................................................................................................................... 5
3.2 PCI Express Interfaces .............................................................................................................................. 5
3.2.1 RDK Configuration Modules and Their Receptacles ......................................................................... 5
3.2.2 PCI Express Lane 0 to Lane 3 ........................................................................................................... 6
3.2.3 PCI Express Lane 4 to Lane 7 ........................................................................................................... 6
3.2.4 PCI Express Lane 8 to Lane 11 ......................................................................................................... 7
3.2.5 PCI Express lane 12 to lane 15 ......................................................................................................... 8
3.3 Reference Clock Circuits ........................................................................................................................... 8
3.4 Reset Circuits ............................................................................................................................................ 9
3.5 Serial Hot-Plug (SHP) Controller Circuits ................................................................................................ 10
3.6 Serial EEPROM ....................................................................................................................................... 11
3.7 I
2
C Interface ............................................................................................................................................. 11
3.8 Power Distribution Circuits ....................................................................................................................... 11
3.9 FPGA Interface ........................................................................................................................................ 12
3.10 LED and 7-Segment Displays ................................................................................................................. 13
3.10.1 LED Indicators ................................................................................................................................. 13
3.10.2 7-Segment Displays ......................................................................................................................... 14
3.11 GPIO Pins ................................................................................................................................................ 15
3.12 Reserved Pins ......................................................................................................................................... 15
4. On-Board Connectors, Switches, and Jumpers ............................................................................................... 16
4.1 DIP Switches ........................................................................................................................................... 16
4.1.1 Dip Switch Group 1 .......................................................................................................................... 16
4.1.2 Dip Switch Group 2 .......................................................................................................................... 17
4.1.3 Dip Switch Group 3 .......................................................................................................................... 19
4.2 Push-Button Switches .............................................................................................................................. 20
4.2.1 Manual Reset# (S1) ......................................................................................................................... 20
4.2.2 FPGA Manual Reset# (S2) .............................................................................................................. 20
4.2.3 Serial Hot-Plug Controller Attention Button (S3) ............................................................................. 21
4.3 Connectors and Headers ......................................................................................................................... 21
4.3.1 ATX Peripheral Power Connectors (J1-J4 & J7-J8) ........................................................................ 21
4.3.2 x4 PCI Express External Cable Connectors (J5 & J6) .................................................................... 21
4.3.3 ATX Main Power Connector (J9) ..................................................................................................... 22
4.3.4 ATX +12V Power Connector(J10) ................................................................................................... 22
4.3.5 Xilinx JTAG Connector (J12) ........................................................................................................... 22
4.3.6 Xilinx Mode Setting Header (J13) .................................................................................................... 23
4.3.7 PEX 8619 JTAG Header (JP3) ........................................................................................................ 23
4.3.8 SMBus Header (JP5) ....................................................................................................................... 23
4.3.9 PCI Express x8 Midbus Probe Footprint (JP6) ................................................................................ 23
4.3.10 PEX 8619 I
2
C Port (JP8) ................................................................................................................. 24
4.3.11 Debug Signal Header (JP9 & JP11) ................................................................................................ 24
4.3.12 Debug Input Header (JP10) ............................................................................................................. 26
4.3.13 Reference Clock Header (JP100) .................................................................................................... 26
5. RDK Port Configurations .................................................................................................................................. 27
6. Bill of Materials/ Schematics ............................................................................................................................ 33
![](https://csdnimg.cn/release/download_crawler_static/11712507/bg5.jpg)
PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2009 by PLX Technology, Inc. All rights reserved iii
FIGURES
Figure 1. PEX 8619BA Base Board RDK Front View ................................................................................................ 2
Figure 2. Connecting The RDK to a PC with x1 or x4 link ......................................................................................... 4
Figure 3. Connecting the RDK to a PC with x8 link ................................................................................................... 4
Figure 4. Lanes 0-3 Hardware Connections on the RDK .......................................................................................... 6
Figure 5. Lanes 4-7 Hardware Connections on the RDK .......................................................................................... 7
Figure 6. Lanes 8-11 Hardware Connections on the RDK ........................................................................................ 7
Figure 7. Lanes 12 – 15 Hardware Connections on the RDK ................................................................................... 8
Figure 8. RDK Reference Clock Circuits ................................................................................................................... 9
Figure 9. RDK Reset Circuits .................................................................................................................................... 9
Figure 10. SERIAL HOT-PLUG Circuits .................................................................................................................. 10
Figure 11. RDK ATX Power Connectors ................................................................................................................. 11
Figure 12. RDK Power Distribution Circuits ............................................................................................................ 12
Figure 13. FPGA Interface on RDK ......................................................................................................................... 13
Figure 14. RDK Dip Switch Groups ......................................................................................................................... 16
Figure 15. Group1 of Switches ................................................................................................................................ 16
Figure 16. Group 2 of Dipswitches .......................................................................................................................... 17
Figure 17. Group 3 of Dip Switches ......................................................................................................................... 19
Figure 18. x1 upstream and 15x1 downstream (PCFG=0000) ............................................................................... 27
Figure 19. x4 upstream 12x1 downstream (PCFG=0001) ...................................................................................... 28
Figure 20. x4 upstream, 1x4 and 8x1 downstream (PCFG=0010) .......................................................................... 29
Figure 21. x4 upstream, 2x4 and 4x1 downstream (PCFG=0011) .......................................................................... 30
Figure 22. x8 upstream, 8x1 downstream (PCFG=0101) ....................................................................................... 31
Figure 23. x8 upstream, 1x4 and 4x1 downstream (PCFG=0110) .......................................................................... 32
TABLES
Table 1. Port Configurations Supported by the RDK ................................................................................................. 5
Table 2. RDK LED Indicator descriptions ................................................................................................................ 13
Table 3. RDK 7-Segment Display Functions ........................................................................................................... 14
Table 4. Strap_Reserved Pin Connections ............................................................................................................. 15
Table 5. Functional Description of Group 1 Dip Switches ....................................................................................... 17
Table 6. Functional Description of Group 2 Dip Switches ....................................................................................... 18
Table 7. Port Configurations use Dipswitch SW2 .................................................................................................... 19
Table 8. Functional Descriptions of SW3, SW6, SW13-SW14 ............................................................................... 20
Table 9. Signal Names of J1-J4 & J7-J8 ................................................................................................................. 21
Table 10. Signal Names of J5 and J6 ...................................................................................................................... 21
Table 11. Signal Names of J9 ................................................................................................................................. 22
Table 12. Signal Names of J10 ............................................................................................................................... 22
Table 13. Signal Names of J12 ............................................................................................................................... 22
Table 14. Signal Names of J13 ............................................................................................................................... 23
Table 15. Pin assignment of JP3 ............................................................................................................................. 23
Table 16. Signal Names of JP5 ............................................................................................................................... 23
Table 17. Signal Names of JP6 ............................................................................................................................... 23
Table 18. Pin assignment of JP8 ............................................................................................................................. 24
Table 19. Pin assignment of JP9 & JP11 ................................................................................................................ 24
Table 20. Pin assignment of JP10 ........................................................................................................................... 26
Table 21. Pin assignment of JP100 ......................................................................................................................... 26
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