PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2009 by PLX Technology, Inc. All rights reserved ii
CONTENTS
NOTICE ......................................................................................................................................................................... i
ABOUT THIS MANUAL ..................................................................................................................................................... i
REVISION HISTORY .................................................................................................................................................... i
1. General Information ........................................................................................................................................... 1
1.1 PEX 8619 Features ................................................................................................................................... 1
1.2 PEX 8619BA-BB RDK Features ................................................................................................................ 3
2. System Architecture ........................................................................................................................................... 4
3. Hardware Architecture ....................................................................................................................................... 5
3.1 PEX 8619 ................................................................................................................................................... 5
3.2 PCI Express Interfaces .............................................................................................................................. 5
3.2.1 RDK Configuration Modules and Their Receptacles ......................................................................... 5
3.2.2 PCI Express Lane 0 to Lane 3 ........................................................................................................... 6
3.2.3 PCI Express Lane 4 to Lane 7 ........................................................................................................... 6
3.2.4 PCI Express Lane 8 to Lane 11 ......................................................................................................... 7
3.2.5 PCI Express lane 12 to lane 15 ......................................................................................................... 8
3.3 Reference Clock Circuits ........................................................................................................................... 8
3.4 Reset Circuits ............................................................................................................................................ 9
3.5 Serial Hot-Plug (SHP) Controller Circuits ................................................................................................ 10
3.6 Serial EEPROM ....................................................................................................................................... 11
3.7 I
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C Interface ............................................................................................................................................. 11
3.8 Power Distribution Circuits ....................................................................................................................... 11
3.9 FPGA Interface ........................................................................................................................................ 12
3.10 LED and 7-Segment Displays ................................................................................................................. 13
3.10.1 LED Indicators ................................................................................................................................. 13
3.10.2 7-Segment Displays ......................................................................................................................... 14
3.11 GPIO Pins ................................................................................................................................................ 15
3.12 Reserved Pins ......................................................................................................................................... 15
4. On-Board Connectors, Switches, and Jumpers ............................................................................................... 16
4.1 DIP Switches ........................................................................................................................................... 16
4.1.1 Dip Switch Group 1 .......................................................................................................................... 16
4.1.2 Dip Switch Group 2 .......................................................................................................................... 17
4.1.3 Dip Switch Group 3 .......................................................................................................................... 19
4.2 Push-Button Switches .............................................................................................................................. 20
4.2.1 Manual Reset# (S1) ......................................................................................................................... 20
4.2.2 FPGA Manual Reset# (S2) .............................................................................................................. 20
4.2.3 Serial Hot-Plug Controller Attention Button (S3) ............................................................................. 21
4.3 Connectors and Headers ......................................................................................................................... 21
4.3.1 ATX Peripheral Power Connectors (J1-J4 & J7-J8) ........................................................................ 21
4.3.2 x4 PCI Express External Cable Connectors (J5 & J6) .................................................................... 21
4.3.3 ATX Main Power Connector (J9) ..................................................................................................... 22
4.3.4 ATX +12V Power Connector(J10) ................................................................................................... 22
4.3.5 Xilinx JTAG Connector (J12) ........................................................................................................... 22
4.3.6 Xilinx Mode Setting Header (J13) .................................................................................................... 23
4.3.7 PEX 8619 JTAG Header (JP3) ........................................................................................................ 23
4.3.8 SMBus Header (JP5) ....................................................................................................................... 23
4.3.9 PCI Express x8 Midbus Probe Footprint (JP6) ................................................................................ 23
4.3.10 PEX 8619 I
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C Port (JP8) ................................................................................................................. 24
4.3.11 Debug Signal Header (JP9 & JP11) ................................................................................................ 24
4.3.12 Debug Input Header (JP10) ............................................................................................................. 26
4.3.13 Reference Clock Header (JP100) .................................................................................................... 26
5. RDK Port Configurations .................................................................................................................................. 27
6. Bill of Materials/ Schematics ............................................................................................................................ 33
