PCI Express
®
Base Specification
Revision 2.1
March 4, 2009
2
Revision Revision History DATE
1.0 Initial release. 07/22/2002
1.0a Incorporated Errata C1-C66 and E1-E4.17. 04/15/2003
1.1 Incorporated approved Errata and ECNs. 03/28/2005
2.0 Added 5.0 GT/s data rate and incorporated approved Errata and ECNs. 12/20/2006
2.1 Incorporated Errata for the PCI Express Base Specification, Rev. 2.0
(February 27, 2009), and added the following ECNs:
• Internal Error Reporting ECN (April 24, 2008)
• Multicast ECN (December 14, 2007, approved by PWG May 8, 2008)
• Atomic Operations ECN (January 15, 2008, approved by PWG April 17,
2008)
• Resizable BAR Capability ECN (January 22, 2008, updated and
approved by PWG April 24, 2008)
• Dynamic Power Allocation ECN (May 24, 2008)
• ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008)
• Latency Tolerance Reporting ECN (22 January 2008, updated 14
August 2008)
• Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last
updated June 4, 2007)
• Extended Tag Enable Default ECN (September 5, 2008)
• TLP Processing Hints ECN (September 11, 2008)
• TLP Prefix ECN (December 15, 2008)
03/04/2009
PCI-SIG
®
disclaims all warranties and liability for the use of this document and the information contained
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make a commitment to update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of this specification.
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DISCLAIMER
This PCI Express Base Specification is provided “as is” with no warranties whatsoever, including any
warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for
infringement of proprietary rights, relating to use of information in this specification. No license, express
or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG.
All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.
Copyright © 2002-2009 PCI-SIG
PCI EXPRESS BASE SPECIFICATION, REV. 2.1
3
Contents
OBJECTIVE OF THE SPECIFICATION.................................................................................... 25
DOCUMENT ORGANIZATION ................................................................................................ 25
DOCUMENTATION CONVENTIONS...................................................................................... 26
TERMS AND ACRONYMS........................................................................................................ 27
REFERENCE DOCUMENTS...................................................................................................... 34
1. INTRODUCTION ................................................................................................................ 35
1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 35
1.2. PCI EXPRESS LINK......................................................................................................... 37
1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 39
1.3.1. Root Complex........................................................................................................ 39
1.3.2. Endpoints .............................................................................................................. 40
1.3.3. Switch.................................................................................................................... 43
1.3.4. Root Complex Event Collector.............................................................................. 44
1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 44
1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION....................................................... 44
1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 45
1.5.1. Transaction Layer................................................................................................. 46
1.5.2. Data Link Layer.................................................................................................... 46
1.5.3. Physical Layer ...................................................................................................... 47
1.5.4. Layer Functions and Services............................................................................... 47
2. TRANSACTION LAYER SPECIFICATION ..................................................................... 51
2.1. T
RANSACTION LAYER OVERVIEW.................................................................................. 51
2.1.1. Address Spaces, Transaction Types, and Usage................................................... 52
2.1.2. Packet Format Overview ...................................................................................... 54
2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 56
2.2.1. Common Packet Header Fields ............................................................................ 56
2.2.2. TLPs with Data Payloads - Rules......................................................................... 59
2.2.3. TLP Digest Rules .................................................................................................. 63
2.2.4. Routing and Addressing Rules.............................................................................. 63
2.2.5. First/Last DW Byte Enables Rules........................................................................ 67
2.2.6. Transaction Descriptor......................................................................................... 70
2.2.7. Memory, I/O, and Configuration Request Rules................................................... 75
2.2.8. Message Request Rules......................................................................................... 81
2.2.9. Completion Rules.................................................................................................. 94
2.2.10. TLP Prefix Rules................................................................................................... 97
2.3. H
ANDLING OF RECEIVED TLPS.................................................................................... 101
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2.3.1. Request Handling Rules...................................................................................... 104
2.3.2. Completion Handling Rules................................................................................ 117
2.4. TRANSACTION ORDERING............................................................................................ 119
2.4.1. Transaction Ordering Rules ............................................................................... 119
2.4.2. Update Ordering and Granularity Observed by a Read Transaction................ 123
2.4.3. Update Ordering and Granularity Provided by a Write Transaction................ 124
2.5. VIRTUAL CHANNEL (VC) MECHANISM........................................................................ 125
2.5.1. Virtual Channel Identification (VC ID).............................................................. 127
2.5.2. TC to VC Mapping.............................................................................................. 128
2.5.3. VC and TC Rules................................................................................................. 129
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 130
2.6.1. Flow Control Rules............................................................................................. 131
2.7. DATA INTEGRITY ......................................................................................................... 141
2.7.1. ECRC Rules ........................................................................................................ 142
2.7.2. Error Forwarding............................................................................................... 146
2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 148
2.9. LINK STATUS DEPENDENCIES ...................................................................................... 149
2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 149
2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 150
3. DATA LINK LAYER SPECIFICATION.......................................................................... 151
3.1. DATA LINK LAYER OVERVIEW .................................................................................... 151
3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 153
3.2.1. Data Link Control and Management State Machine Rules ................................ 154
3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 156
3.3.1. Flow Control Initialization State Machine Rules ............................................... 156
3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 160
3.4.1. Data Link Layer Packet Rules ............................................................................ 160
3.5. DATA INTEGRITY ......................................................................................................... 165
3.5.1. Introduction......................................................................................................... 165
3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 165
3.5.3. LCRC and Sequence Number (TLP Receiver).................................................... 178
4. PHYSICAL LAYER SPECIFICATION............................................................................ 187
4.1. I
NTRODUCTION ............................................................................................................ 187
4.2. LOGICAL SUB-BLOCK................................................................................................... 187
4.2.1. Symbol Encoding ................................................................................................ 188
4.2.2. Framing and Application of Symbols to Lanes................................................... 191
4.2.3. Data Scrambling................................................................................................. 194
4.2.4. Link Initialization and Training.......................................................................... 196
4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 208
4.2.6. Link Training and Status State Rules.................................................................. 212
4.2.7. Clock Tolerance Compensation.......................................................................... 258
4.2.8. Compliance Pattern ............................................................................................ 260
4.2.9. Modified Compliance Pattern............................................................................. 261
4.3. ELECTRICAL SUB-BLOCK ............................................................................................. 262
4.3.1. Maintaining Backwards Compatibility............................................................... 262
PCI EXPRESS BASE SPECIFICATION, REV. 2.1
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4.3.2. Jitter Budgeting and Measurement..................................................................... 264
4.3.3. Transmitter Specification.................................................................................... 265
4.3.4. Receiver Specification......................................................................................... 281
4.3.5. Transmitter and Receiver DC Specifications...................................................... 293
4.3.6. Channel Specifications........................................................................................ 298
4.3.7. Reference Clock Specifications........................................................................... 305
5. POWER MANAGEMENT................................................................................................. 313
5.1. OVERVIEW ................................................................................................................... 313
5.1.1. Statement of Requirements.................................................................................. 314
5.2. LINK STATE POWER MANAGEMENT............................................................................. 314
5.3. PCI-PM SOFTWARE COMPATIBLE MECHANISMS......................................................... 319
5.3.1. Device Power Management States (D-States) of a Function.............................. 319
5.3.2. PM Software Control of the Link Power Management State.............................. 323
5.3.3. Power Management Event Mechanisms............................................................. 329
5.4. NATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS....................................... 336
5.4.1. Active State Power Management (ASPM) .......................................................... 336
5.5. AUXILIARY POWER SUPPORT....................................................................................... 353
5.5.1. Auxiliary Power Enabling................................................................................... 353
5.6. POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 354
6. SYSTEM ARCHITECTURE ............................................................................................. 357
6.1. INTERRUPT AND PME SUPPORT ................................................................................... 357
6.1.1. Rationale for PCI Express Interrupt Model........................................................ 357
6.1.2. PCI Compatible INTx Emulation........................................................................ 358
6.1.3. INTx Emulation Software Model ........................................................................ 358
6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 358
6.1.5. PME Support....................................................................................................... 360
6.1.6. Native PME Software Model .............................................................................. 360
6.1.7. Legacy PME Software Model ............................................................................. 361
6.1.8. Operating System Power Management Notification........................................... 361
6.1.9. PME Routing Between PCI Express and PCI Hierarchies ................................ 361
6.2. E
RROR SIGNALING AND LOGGING................................................................................ 362
6.2.1. Scope................................................................................................................... 362
6.2.2. Error Classification............................................................................................ 362
6.2.3. Error Signaling................................................................................................... 364
6.2.4. Error Logging..................................................................................................... 371
6.2.5. Sequence of Device Error Signaling and Logging Operations .......................... 376
6.2.6. Error Message Controls ..................................................................................... 378
6.2.7. Error Listing and Rules ...................................................................................... 379
6.2.8. Virtual PCI Bridge Error Handling.................................................................... 384
6.2.9. Internal Errors.................................................................................................... 386
6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 386
6.3.1. Introduction and Scope....................................................................................... 386
6.3.2. TC/VC Mapping and Example Usage................................................................. 387
6.3.3. VC Arbitration .................................................................................................... 389
6.3.4. Isochronous Support........................................................................................... 397
