AT32UC3A0_A1英文资料

Features

• High Performance, Low Power 32-Bit Atmel

– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performing 1.49 DMIPS / MHz

– Memory Protection Unit

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 4ms Page Programming Time and 8ms Full-Chip Erase Time

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

• Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)

• External Memory Interface on AT32UC3A0 Derivatives

– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)

• Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed

– Flexible End-Point Configuration and Management with Dedicated DMA Channels

– On-chip Transceivers Including Pull-Ups

• Ethernet MAC 10/100 Mbps interface

– 802.3 Ethernet Media Access Controller

– Supports Media Independent Interface (MII) and Reduced MII (RMII)

• One Three-Channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities

• One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)

• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

• One 8-channel 10-bit Analog-To-Digital Converter

• 16-bit Stereo Audio Bitstream

– Sample Rate Up to 50 KHz

32-Bit Atmel AVR

Microcontroller

AT32UC3A0512

AT32UC3A0256

AT32UC3A0128

AT32UC3A1512

AT32UC3A1256

• On-Chip Debug System (JTAG interface)

– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace

• 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins) , 144 BGA (109 GPIO pins)

• 5V Input Tolerant I/Os

• Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply

1. Description

The AT32UC3A incorporates on-chip Flash and SRAM memories for secure and fast access.

For applications requiring additional memory, an external memory interface is provided on

AT32UC3A0 derivatives.

The Peripheral Direct Memory Access controller (PDCA) enables data transfers between periph-

erals and memories without processor involvement. PDCA drastically reduces processing

overhead when transferring continuous and large data streams between modules within the

The PowerManager improves design flexibility and security: the on-chip Brown-Out Detector

oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.

The AT32UC3A also features many communication interfaces for communication intensive

applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like

flexible Synchronous Serial Controller, USB and Ethernet MAC are available.

The Synchronous Serial Controller provides easy access to serial communication protocols and

audio standards like I2S.

The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time

thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device

like a USB Flash disk or a USB printer to be directly connected to the processor.

provides on-chip solutions for network-connected devices.

The table below lists all AT32UC3A memory and package configurations:

• MPU: Memory Protection Unit

• OCD: On Chip Debug

• PB: Peripheral Bus

• PDCA: Peripheral Direct Memory Access Controller (PDC) version A

• USBB: USB On-The-GO Controller version B

Device Flash SRAM Ext. Bus Interface

Ethernet

AT32UC3A0512 512 Kbytes 64 Kbytes yes yes 144 pin LQFP

AT32UC3A0256 256 Kbytes 64 Kbytes yes yes 144 pin LQFP