03 | Keysight | Quick Start Guide for ADS in Power Electronics - Demo Guide
When to Worry About Layout Parasitics Inductance?
Rule of Thumb: “If the rise/fall time of the switch loop edges in nanoseconds approaches the
quantity on the left (vacuum permeability 1.26 nH/mm times effective switched loop length in
mm divided by load resistance in ohms), then layout parasitic will be a concern. We recommend
you use ADS to add EM-based model of your PCB traces into your circuit simulation.”
For such a planar loop and with typical circuit values (lloop = 1-10 mm, Rload = 0.1-1.0 ohm),
problems begin as the rise time, τ, approaches tens of nanoseconds. The key point here is
that ADS has a built in electromagnetic (EM) field solver allows you to extract an EM-based
model of the layout parasitics. You can co-simulate regular SPICE-like lumped elements along
with the effects of the layout. You can plot the voltage spikes and do "what if..." design space
exploration, such as using a ground plane for the return current, to minimize their effects.
(See http://www.keysight.com/find/eesof-how-to-estimate-voltage-spikes)
ADS Offers an EM-Based Model of Layout Parasitics
For example, in the below circuit, the spike voltage in the switch loop gets larger and larger as
di/dt gets larger.
Current loops: Layout view
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