CPRI
CPRI Specification V4.2 (2010-09-29)2
Table of Contents
1. Introduction ...................................................................................................................4
2. System Description.......................................................................................................6
2.1. Definitions/Nomenclature...............................................................................6
2.2. System Architecture........................................................................................9
2.3. Reference Configurations.............................................................................10
2.4. Functional Description..................................................................................13
2.4.1. Radio Functionality ............................................................................13
2.4.2. CPRI Control Functionality ................................................................14
3. Interface Baseline........................................................................................................15
3.1. Supported Radio Standards.........................................................................15
3.2. Operating Range............................................................................................15
3.3. Topology/Switching/Multiplexing ................................................................15
3.4. Bandwidth/Capacity/Scalability ...................................................................17
3.4.1. Capacity in terms of Antenna-Carriers...............................................17
3.4.2. Required U-plane IQ Sample Widths.................................................18
3.4.3. Required C&M-plane Bit Rate ...........................................................19
3.5. Synchronization/Timing................................................................................19
3.5.1. Frequency Synchronization ...............................................................19
3.5.2. Frame Timing Information .................................................................20
3.5.3. Link Timing Accuracy ........................................................................21
3.5.4. Round Trip Delay Accuracy...............................................................21
3.5.5. Accuracy of TDD Tx-Rx switching point ............................................22
3.6. Delay Calibration ...........................................................................................22
3.6.1. Round Trip Cable Delay per Link ......................................................22
3.6.2. Round Trip Delay of a Multi-hop Connection.....................................23
3.7. Link Maintenance ..........................................................................................23
3.8. Quality of Service ..........................................................................................24
3.8.1. Maximum Delay.................................................................................24
3.8.2. Bit Error Ratio U-plane ......................................................................24
3.8.3. Bit Error Ratio C&M-plane .................................................................24
3.9. Start-up Requirement....................................................................................25
3.9.1. Clock Start-up Time Requirement .....................................................25
3.9.2. Plug and Play Requirement...............................................................25
4. Interface Specification................................................................................................27
4.1. Protocol Overview.........................................................................................27
4.2. Physical Layer (Layer 1) Specification........................................................28
4.2.1. Line Bit Rate ......................................................................................28
4.2.2. Physical Layer Modes .......................................................................28
4.2.3. Electrical Interface .............................................................................30
4.2.4. Optical Interface ................................................................................30
4.2.5. Line Coding .......................................................................................30
4.2.6. Bit Error Correction/Detection............................................................30
4.2.7. Frame Structure.................................................................................30
4.2.8. Synchronisation and Timing ..............................................................55
4.2.9. Link Delay Accuracy and Cable Delay Calibration ............................56
4.2.10. Link Maintenance of Physical Layer ..................................................59
4.3. Data Link Layer (Layer 2) Specification for Slow C&M Channel...............64
4.3.1. Layer 2 Framing ................................................................................64
4.3.2. Media Access Control/Data Mapping ................................................64
4.3.3. Flow Control ......................................................................................65
4.3.4. Control Data Protection/ Retransmission Mechanism .......................65
4.4. Data Link Layer (Layer 2) Specification for Fast C&M Channel................65
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2010-12-01
16:02:04
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chxjy2012-09-19介绍很详细，很有帮助，谢谢！
