The World Leader in High Performance Signal Processing Solutions
ADSP-BF533 Serial
Communications
Support Email: china.dsp@analog.com
2
BF533 Serial Communications
Three Serial Comm’s Peripherals
SPORTs (synchronous Serial PORTs)
z High Speed (up to SCLK/2)
z Two SPORTs (SPORT0 and SPORT1)
z Typically used for interfacing with CODEC’s and TDM data streams
SPI (Serial Peripheral Interface)
z Single High Speed SPI port (up to SCLK/4)
z Typically used to interface with serial EPROMS, other CPUs, data
converters, and displays
UART (Universal Asynchronous Receiver/Transmitter)
z Single PC-style UART port (baud rate up to SCLK/16)
z Typically used for maintenance port, and interfacing with slow
serial peripherals
3
ADSP-BF533 SPORTs
Two synchronous serial ports
z Fully independent receive and transmit channels - double
buffered
z Primary and Secondary Data RX/TX pins
z Support up to 32-bit serial words
z Internal or externally generated serial clocks and frame
syncs
z Programmable internal/external frame syncs
z Built in hardware for u-law & A-law companding
z Support for multichannel interfaces
z I
2
S signaling support
z Generates optional interrupts
z Separate Data and Error Interrupts
z Operates up to ½ System bus clock rate (SCLK)
4
ADSP-BF533 Serial PORTs Features
Interrupt-driven, single-word transfers to/from on-chip
memory controlled by ADSP-BF533 core
Block word transfers to/from memory controlled by DMA
controller
Several modes of operation
z Programmable serial word length, 3 to 32-bits
z Either MSB or LSB first
z Early Frame Sync
z Late Frame Sync
z No Frame Sync
z 128 time slot out of a 1024-channel window multi-channel
capability for TDM interfaces
z I2S capable operation
5
ADSP-BF533 SPORT Pins
Pin Description
DTxPRI Transmit Data Primary
DTxSEC Transmit Data Secondary
TSCLKx Transmit Clock
TFSx Transmit Frame Sync
DRxPRI Receive Data Primary
DRxSEC Receive Data Secondary
RSCLKx Receive Clock
RFSx Receive Frame Sync
