sequence

1.1 I

2

C master sequencer

The I

2

C master sequencer is designed to run through a set of instructions programmed

beforehand into an instruction FIFO. For read operations the read data is written into a FIFO for

later retrieval.

Figure 1. I

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C Byte Stream Code

A one-byte read operation has the instruction code 0x80, while a 5-byte read operation has the

code 0x84. A one byte write operation has the instruction sequence 0x80 0xXX, where XX is

the data to be written. Similarly, a 3 byte write operation has the instruction sequence 0x82

0xXX 0xYY 0xZZ.

The sequencer can be paused. The duration is specified in units of 32 ticks, with each tick

being ¼ of the SCL clock width. So 32 ticks equal the time of an 8-bit data transfer (sans ack).

You can delay up to 16 units per instruction.

Table 1. I

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C master sequencer registers

0x30 CTL R/W CTL[2]: clear the FIFOs

0x00

0x31 STAT R/O STAT[7:1]: reserved

0x00

0x32 THROTTLE R/W Use this to adjust the target SCL speed.

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