Table of Contents
Features.......................................................................................................................... 1
1. Configuration Summary...........................................................................................17
2. Ordering Information................................................................................................19
3. Block Diagram......................................................................................................... 20
3.1. SAM D5x/E5x Block Diagram.....................................................................................................20
4. Pinout...................................................................................................................... 22
4.1. 48-Pin VQFN Package............................................................................................................... 22
4.2. 64-Pin TQFP and VQFN Package............................................................................................. 23
4.3. 64-Pin WLCSP Package............................................................................................................ 24
4.4. 100-Pin TQFP Package............................................................................................................. 25
4.5. 120-ball TFBGA Package...........................................................................................................26
4.6. 128-Pin TQFP Package............................................................................................................. 27
5. Signal Descriptions List........................................................................................... 28
6. I/O Multiplexing and Considerations........................................................................32
6.1. Multiplexed Signals.................................................................................................................... 32
6.2. Other Functions..........................................................................................................................36
7. Power Supply and Start-Up Considerations............................................................ 47
7.1. Power Domain Overview............................................................................................................47
7.2. Power Supply Considerations.................................................................................................... 47
7.3. Power-Up................................................................................................................................... 49
7.4. Power-On Reset and Brown-Out Detector................................................................................. 50
8. Product Memory Mapping Overview....................................................................... 52
9. Memories.................................................................................................................54
9.1. Embedded Memories................................................................................................................. 54
9.2. Physical Memory Map................................................................................................................ 54
9.3. SRAM Memory Configuration.....................................................................................................55
9.4. NVM User Page Mapping...........................................................................................................57
9.5. NVM Software Calibration Area Mapping...................................................................................59
9.6. Serial Number............................................................................................................................ 60
10. Processor and Architecture..................................................................................... 61
10.1. Cortex M4 Processor..................................................................................................................61
10.2. Nested Vector Interrupt Controller..............................................................................................64
10.3. High-Speed Bus System............................................................................................................ 77
11. CMCC - Cortex M Cache Controller........................................................................ 81
11.1. Overview.................................................................................................................................... 81
SAM D5x/E5x Family Data Sheet
© 2019 Microchip Technology Inc.
Datasheet
DS60001507E-page 5
