Section number Title Page
5.2 Device security..............................................................................................................................................................89
5.2.1 Flash memory security...................................................................................................................................89
5.2.2 Cryptographic Services Engine (CSEc) security features..............................................................................90
5.2.3 Device Boot modes........................................................................................................................................ 91
5.3 Security use case examples...........................................................................................................................................91
5.3.1 Secure boot: check bootloader for integrity and authenticity........................................................................ 91
5.3.2 Chain of trust: check flash memory for integrity and authenticity................................................................ 92
5.3.3 Secure communication...................................................................................................................................93
5.3.4 Component protection....................................................................................................................................94
5.3.5 Message-authentication example................................................................................................................... 95
5.4 Steps required before failure analysis...........................................................................................................................96
5.5 Security programming flow example (Secure Boot).................................................................................................... 97
Chapter 6
Safety Overview
6.1 Introduction...................................................................................................................................................................99
6.2 S32K1xx safety concept............................................................................................................................................... 100
6.2.1 Cortex-M4/M0+ Structural Core Self Test (SCST).......................................................................................101
6.2.2 ECC on RAM and flash memory...................................................................................................................102
6.2.3 Power supply monitoring...............................................................................................................................102
6.2.4 Clock monitoring........................................................................................................................................... 103
6.2.5 Temporal protection.......................................................................................................................................103
6.2.6 Operational interference protection............................................................................................................... 103
6.2.7 CRC................................................................................................................................................................105
6.2.8 Diversity of system resources........................................................................................................................ 105
Chapter 7
CM4 Overview
7.1 Arm Cortex-M4F core configuration............................................................................................................................107
7.1.1 Buses, interconnects, and interfaces.............................................................................................................. 108
7.1.2 System Tick Timer.........................................................................................................................................108
S32K1xx Series Reference Manual, Rev. 7, 04/2018
NXP Semiconductors 5