Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 3B:
System Programming Guide, Part 2
NOTE: The Intel
®
64 and IA-32 Architectures Software Developer's Manual
consists of five volumes: Basic Architecture, Order Number 253665;
Instruction Set Reference A-M, Order Number 253666; Instruction Set
Reference N-Z, Order Number 253667; System Programming Guide,
Part 1, Order Number 253668; System Programming Guide, Part 2, Order
Number 253669. Refer to all five volumes when evaluating your design
needs.
Order Number: 253669-029US
November 2008
ii Vol. 3B
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANT-
ED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH
PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR IN-
TENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUA-
TION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers
must not rely on the absence or characteristics of any features or instructions marked "reserved" or "unde-
fined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them. The information here is subject to change without no-
tice. Do not finalize a design with this information.
The Intel
®
64 architecture processors may contain design defects or errors known as errata. Current char-
acterized errata are available on request.
Intel
®
Hyper-Threading Technology requires a computer system with an Intel
®
processor supporting Intel
Hyper-Threading Technology and an Intel
®
HT Technology enabled chipset, BIOS and operating system.
Performance will vary depending on the specific hardware and software you use. For more information, see
http://www.intel.com/technology/hyperthread/index.htm; including details on which processors support Intel HT
Technology.
Intel
®
Virtualization Technology requires a computer system with an enabled Intel
®
processor, BIOS, virtual
machine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, perfor-
mance or other benefits will
vary depending on hardware and software configurations. Intel
®
Virtualization
Technology-enabled BIOS and VMM applications are currently in development.
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, oper-
ating system, device drivers and applications enabled for Intel
®
64 architecture. Processors will not operate
(including 32-bit operation) without an Intel
®
64 architecture-enabled BIOS. Performance will vary depend-
ing on your hardware and software configurations. Consult with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability
and a supporting operating system. Check with your PC manufacturer on whether your system delivers Ex-
ecute Disable Bit functionality.
Intel, Pentium, Intel Xeon, Intel NetBurst, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo, Intel Core 2
Extreme, Intel Pentium D, Itanium, Intel SpeedStep, MMX, Intel Atom, and VTune are trademarks or reg-
istered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing
your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained by calling 1-800-548-4725, or by visiting Intel’s website at http://www.intel.com
Copyright © 1997-2008 Intel Corporation
Vol. 3 18-1
CHAPTER 18
DEBUGGING AND PERFORMANCE MONITORING
Intel 64 and IA-32 architectures provide debug facilities for use in debugging code
and monitoring performance. These facilities are valuable for debugging application
software, system software, and multitasking operating systems. Debug support is
accessed using debug registers (DB0 through DB7) and model-specific registers
(MSRs):
• Debug registers hold the addresses of memory and I/O locations called break-
points. Breakpoints are user-selected locations in a program, a data-storage area
in memory, or specific I/O ports. They are set where a programmer or system
designer wishes to halt execution of a program and examine the state of the
processor by invoking debugger software. A debug exception (#DB) is generated
when a memory or I/O access is made to a breakpoint address.
• MSRs monitor branches, interrupts, and exceptions; they record addresses of the
last branch, interrupt or exception taken and the last branch taken before an
interrupt or exception.
18.1 OVERVIEW OF DEBUG SUPPORT FACILITIES
The following processor facilities support debugging and performance monitoring:
• Debug exception (#DB) — Transfers program control to a debug procedure or
task when a debug event occurs.
• Breakpoint exception (#BP) — See breakpoint instruction (INT 3) below.
• Breakpoint-address registers (DR0 through DR3) — Specifies the
addresses of up to 4 breakpoints.
• Debug status register (DR6) — Reports the conditions that were in effect
when a debug or breakpoint exception was generated.
• Debug control register (DR7) — Specifies the forms of memory or I/O access
that cause breakpoints to be generated.
• T (trap) flag, TSS — Generates a debug exception (#DB) when an attempt is
made to switch to a task with the T flag set in its TSS.
• RF (resume) flag, EFLAGS register — Suppresses multiple exceptions to the
same instruction.
• TF (trap) flag, EFLAGS register — Generates a debug exception (#DB) after
every execution of an instruction.
• Breakpoint instruction (INT 3) — Generates a breakpoint exception (#BP)
that transfers program control to the debugger procedure or task. This
instruction is an alternative way to set code breakpoints. It is especially useful
18-2 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
when more than four breakpoints are desired, or when breakpoints are being
placed in the source code.
• Last branch recording facilities — Store branch records in the last branch
record (LBR) stack MSRs for the most recent taken branches, interrupts, and/or
exceptions in MSRs. A branch record consist of a branch-from and a branch-to
instruction address. Send branch records out on the system bus as branch trace
messages (BTMs).
These facilities allow a debugger to be called as a separate task or as a procedure in
the context of the current program or task. The following conditions can be used to
invoke the debugger:
• Task switch to a specific task.
• Execution of the breakpoint instruction.
• Execution of any instruction.
• Execution of an instruction at a specified address.
• Read or write to a specified memory address/range.
• Write to a specified memory address/range.
• Input from a specified I/O address/range.
• Output to a specified I/O address/range.
• Attempt to change the contents of a debug register.
18.2 DEBUG REGISTERS
Eight debug registers (see Figure 18-1) control the debug operation of the processor.
These registers can be written to and read using the move to/from debug register
form of the MOV instruction. A debug register may be the source or destination
operand for one of these instructions.
Debug registers are privileged resources; a MOV instruction that accesses these
registers can only be executed in real-address mode, in SMM or in protected mode at
a CPL of 0. An attempt to read or write the debug registers from any other privilege
level generates a general-protection exception (#GP).
The primary function of the debug registers is to set up and monitor from 1 to 4
breakpoints, numbered 0 though 3. For each breakpoint, the following information
can be specified:
• The linear address where the breakpoint is to occur.
• The length of the breakpoint location (1, 2, or 4 bytes).
• The operation that must be performed at the address for a debug exception to be
generated.
• Whether the breakpoint is enabled.
Vol. 3 18-3
DEBUGGING AND PERFORMANCE MONITORING
• Whether the breakpoint condition was present when the debug exception was
generated.
The following paragraphs describe the functions of flags and fields in the debug
registers.
Figure 18-1. Debug Registers
31
24
23
22
21 20 19 16
15
13
14 12
11
87
0
DR7
L
Reserved
0
123456
910
1718
252627282930
G
0
L
1
L
2
L
3
G
3
L
E
G
E
G
2
G
1
0 0
G
D
R/W
0
LEN
0
R/W
1
LEN
1
R/W
2
LEN
2
R/W
3
LEN
3
31
16
15
13
14 12 11
8
7
0
DR6
B
0
123456
910
B
1
B
2
B
3
0111111111
B
D
B
S
B
T
31
0
DR5
31
0
DR4
31
0
DR3
Breakpoint 3 Linear Address
31
0
DR2Breakpoint 2 Linear Address
31
0
DR1
Breakpoint 1 Linear Address
31
0
DR0Breakpoint 0 Linear Address
001
Reserved (set to 1)
