STANDARD FOR
PROPERTY SPECIFICATION VOLTAGE (PSL)
1. Overview
1.1 Scope
This standard defines the property specification language (PSL), which formally describes electronic system
behavior. This standard specifies the syntax and semantics for PSL and also clarifies how PSL interfaces
with various standard electronic system design languages.
1.2 Purpose
The purpose of this standard is to provide a well-defined language for formal specification of electronic
system behavior, one that is compatible with multiple electronic system design languages, including IEEE
Std 1076™ (VHDL), IEEE Std 1364™ (Verilog®), IEEE P1800™1 (SystemVerilog®), and IEEE P1666™
(SystemC), to facilitate a common specification and verification flow for multi-language and mixedlanguage
designs.
1.2.1 Background
The complexity of Very Large Scale Integration (VLSI) has grown to such a degree that traditional
approaches have begun to reach their limitations, and verification costs have reached 60%–70% of
development resources. The need for advanced verification methodology, with improved observability of
design behavior and improved controllability of the verification process, has become critical. Over the last
decade, a methodology based on the notion of “properties” has been identified as a powerful verification
paradigm that can assure enhanced productivity, higher design quality and, ultimately, faster time to market
and higher value to engineers and end-users of electronics products. Properties, as used in this context, are
concise, declarative, expressive and unambiguous specifications of desired system behavior, that are used to
guide the verification process. IEEE Std 1850 PSL is a standard language for specifying electronic system
behavior using properties. PSL facilitates property-based verification using both simulation and formal
verification, thereby enabling a productivity boost in functional verification.
