SOLUTIONS MANUAL
COMPUTER ORGANIZATION AND
ARCHITECTURE
DESIGNING FOR PERFORMANCE
SEVENTH EDITION
WILLIAM STALLINGS
Copyright 2005: William Stallings
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© 2005 by William Stallings
All rights reserved. No part of this document may
be reproduced, in any form or by any means, or
posted on the Internet, without permission in
writing from the author.
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NOTICE
This manual contains solutions to all of the review questions and
homework problems in Computer Organization and Architecture,
Seventh Edition. If you spot an error in a solution or in the wording of a
problem, I would greatly appreciate it if you would forward the
information via email to ws@shore.net. An errata sheet for this manual,
if needed, is available at WilliamStallings.com
W.S.
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TABLE OF CONTENTS
Chapter 2: Computer Evolution and Performance
.....................................................
5
Chapter 3: Computer Function and Interconnection
.................................................
9
Chapter 4: Cache Memory
............................................................................................
14
Chapter 5: Internal Memory
........................................................................................
27
Chapter 6: External Memory
........................................................................................
33
Chapter 7: Input/Output
.............................................................................................
37
Chapter 8: Operating System Support
.......................................................................
43
Chapter 9: Computer Arithmetic
................................................................................
48
Chapter 10: Instruction Sets: Characteristics and Functions
.....................................
61
Chapter 11: Instruction Sets: Addressing Modes and Formats
................................
72
Chapter 12: Processor Structure and Function
............................................................
77
Chapter 13: Reduced Instruction Set Computers (RISCs)
.........................................
83
Chapter 14: Instruction-Level Parallelism and Superscalar Processors
..................
87
Chapter 15: The IA-64 Architecture
..............................................................................
93
Chapter 16: Control Unit Operation
.............................................................................
97
Chapter 17: Microprogrammed Control
....................................................................
100
Chapter 18: Parallel Processing
...................................................................................
103
Appendix A: Number Systems
......................................................................................
112
Appendix B: Digital Logic
..............................................................................................
113
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A
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Q
Q
UESTIONS
UESTIONS
2.1 In a stored program computer, programs are represented in a form suitable for
storing in memory alongside the data. The computer gets its instructions by reading
them from memory, and a program can be set or altered by setting the values of a
portion of memory.
2.2 A main memory, which stores both data and instructions: an arithmetic and logic
unit (ALU) capable of operating on binary data; a control unit, which interprets the
instructions in memory and causes them to be executed; and input and output
(I/O) equipment operated by the control unit.
2.3 Gates, memory cells, and interconnections among gates and memory cells.
2.4 Moore observed that the number of transistors that could be put on a single chip
was doubling every year and correctly predicted that this pace would continue into
the near future.
2.5 Similar or identical instruction set: In many cases, the same set of machine
instructions is supported on all members of the family. Thus, a program that
executes on one machine will also execute on any other. Similar or identical
operating system: The same basic operating system is available for all family
members. Increasing speed: The rate of instruction execution increases in going
from lower to higher family members. Increasing Number of I/O ports: In going
from lower to higher family members. Increasing memory size: In going from
lower to higher family members. Increasing cost: In going from lower to higher
family members.
2.6 In a microprocessor, all of the components of the CPU are on a single chip.
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P
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ROBLEMS
ROBLEMS
2.1 This program is developed in [HAYE98]. The vectors A, B, and C are each stored in
1,000 contiguous locations in memory, beginning at locations 1001, 2001, and 3001,
respectively. The program begins with the left half of location 3. A counting
variable N is set to 999 and decremented after each step until it reaches –1. Thus,
the vectors are processed from high location to low location.
CHAPTER 2
COMPUTER EVOLUTION AND
PERFORMANCE
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