4 Intel
®
I/O Controller Hub 9 (ICH9) Family Datasheet
5.1.3 Parity Error Detection and Generation......................................................111
5.1.4 PCIRST# .............................................................................................112
5.1.5 Peer Cycles..........................................................................................112
5.1.6 PCI-to-PCI Bridge Model........................................................................112
5.1.7 IDSEL to Device Number Mapping...........................................................113
5.1.8 Standard PCI Bus Configuration Mechanism..............................................113
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5)................................................113
5.2.1 Interrupt Generation.............................................................................113
5.2.2 Power Management...............................................................................114
5.2.2.1 S3/S4/S5 Support...................................................................114
5.2.2.2 Resuming from Suspended State...............................................114
5.2.2.3 Device Initiated PM_PME Message .............................................114
5.2.2.4 SMI/SCI Generation.................................................................115
5.2.3 SERR# Generation................................................................................115
5.2.4 Hot-Plug..............................................................................................116
5.2.4.1 Presence Detection..................................................................116
5.2.4.2 Message Generation ................................................................116
5.2.4.3 Attention Button Detection .......................................................117
5.2.4.4 SMI/SCI Generation.................................................................117
5.3 Gigabit Ethernet Controller (B0:D25:F0) .............................................................117
5.3.1 Gigabit Ethernet PCI Bus Interface..........................................................118
5.3.1.1 Transaction Layer....................................................................118
5.3.1.2 Data Alignment.......................................................................118
5.3.1.3 Configuration Request Retry Status ...........................................119
5.3.2 Error Events and Error Reporting ............................................................119
5.3.2.1 Data Parity Error.....................................................................119
5.3.2.2 Completion with Unsuccessful Completion Status.........................119
5.3.3 Ethernet Interface ................................................................................119
5.3.3.1 MAC/LAN Connect Interface......................................................119
5.3.4 PCI Power Management.........................................................................120
5.3.4.1 Wake-Up................................................................................120
5.3.5 Configurable LEDs.................................................................................121
5.3.6 Function Level Reset Support (FLR).........................................................122
5.3.6.1 FLR Steps...............................................................................122
5.4 LPC Bridge (w/ System and Management Functions) (D31:F0)...............................123
5.4.1 LPC Interface .......................................................................................123
5.4.1.1 LPC Cycle Types......................................................................124
5.4.1.2 Start Field Definition................................................................124
5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR).....................................125
5.4.1.4 Size.......................................................................................125
5.4.1.5 SYNC.....................................................................................126
5.4.1.6 SYNC Time-Out.......................................................................126
5.4.1.7 SYNC Error Indication ..............................................................126
5.4.1.8 LFRAME# Usage......................................................................127
5.4.1.9 I/O Cycles..............................................................................127
5.4.1.10 Bus Master Cycles ...................................................................127
5.4.1.11 LPC Power Management...........................................................127
5.4.1.12 Configuration and Intel
®
ICH9 Implications.................................128
5.5 DMA Operation (D31:F0) ..................................................................................128
5.5.1 Channel Priority....................................................................................129
5.5.1.1 Fixed Priority..........................................................................129
5.5.1.2 Rotating Priority......................................................................129
5.5.2 Address Compatibility Mode ...................................................................129
5.5.3 Summary of DMA Transfer Sizes.............................................................130
5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words130
5.5.4 Autoinitialize........................................................................................130
5.5.5 Software Commands.............................................................................131
