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Copyright © 2001 by the Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. Published 23 July 2001. Printed in the United States of America.
Print: ISBN 0-7381-2944-5 SH94949
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IEEE Std 1149.1-2001
(Revision of IEEE Std 1149.1-1990)
IEEE Standard Test Access Port and
Boundary-Scan Architecture
Sponsor
Test Technology Standards Committee
of the
IEEE Computer Society
Approved 14 June 2001
IEEE-SA Standards Board
Abstract: Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and
support of assembled printed circuit boards is defined. The circuitry includes a standard interface
through which instructions and test data are communicated. A set of test features is defined,
including a boundary-scan register, such that the component is able to respond to a minimum set
of instructions designed to assist with testing of assembled printed circuit boards. Also, a language
is defined that allows rigorous description of the component-specific aspects of such testability
features.
Keywords: boundary scan, boundary-scan architecture, Boundary-Scan Description Language,
boundary-scan register, BSDL, circuit boards, circuitry, integrated circuit, printed circuit boards,
TAP, test, test access port, VHDL, VHSIC Hardware Description Language
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Copyright © 2001 IEEE. All rights reserved. iii
Introduction
(This introduction is not part of IEEE Std 1149.1-2001, Standard Test Access Port and Boundary-Scan Architecture.)
This standard defines a test access port and boundary-scan architecture for digital integrated circuits and for
the digital portions of mixed analog/digital integrated circuits. The facilities defined by the standard seek to
provide a solution to the problem of testing assembled printed circuit boards and other products based on
highly complex digital integrated circuits and high-density surface-mounting assembly techniques. They
also provide a means of accessing and controlling design-for-test features built into the digital integrated cir-
cuits themselves. Such features might, for example, include internal scan paths and self-test functions as
well as other features intended to support service applications in the assembled product.
History of the development of this standard
The process of developing this standard began in 1985, when the Joint European Test Action Group
(JETAG) was formed in Europe. During 1986, this group expanded to include members from both Europe
and North America and, as a result, was renamed the Joint Test Action Group (JTAG). Between 1986 and
1988, the JTAG Technical Subcommittee developed and published a series of proposals for a standardized
form of boundary scan. In 1988, the last of these proposals—JTAG Version 2.0—was offered to the IEEE
Testability Bus Standards Committee (P1149) for inclusion in the standard then under development. The
Testability Bus Standards Committee accepted this approach. It decided that the JTAG proposal should
become the basis of a standard within the Testability Bus family, with the result that the P1149.1 project was
initiated. Following these decisions, the JTAG Technical Subcommittee became the core of the IEEE Work-
ing Group that developed this standard.
After the initial approval of this standard in February 1990 and its subsequent publication, the Working
Group immediately began efforts to develop a supplement for the purpose of correction, clarification, and
enhancement. This effort, spurred and guided by interaction between developers and users of the original
standard, culminated in IEEE Std 1149.1a-1993, which was approved in June 1993.
The major changes to this standard introduced by IEEE Std 1149.1a-1993 were
— The addition of two optional instructions, CLAMP and HIGHZ, which standardized the names and
specifications of features often implemented as design-specific features
— The addition of an optional facility to switch a component from a mode in which it complies to this
standard into one in which it supports another design-for-test approach
Further, starting with a proposal made by Kenneth P. Parker and Stig Oresjo in 1990, an effort was under-
taken to develop a language to describe components that conform to this standard. This effort concluded in
the approval of IEEE Std 1149.1b-1994 in September 1994.
The major change introduced to this standard by IEEE Std 1149.1b-1994 was the addition of Annex B,
which defines the Boundary-Scan Description Language. All other changes were minor and were strictly for
clarification.
Changes introduced by this revision
This revision is primarily a housekeeping update, designed to consolidate learning from the first 10 years of
the standard’s use into the standard document.
iv Copyright © 2001 IEEE. All rights reserved.
The principal changes introduced are
— To reduce the risk of accidental entry into test mode, the requirement that a binary code for the
EXTEST instruction be {000...0} has been removed and use of this binary code for other instruc-
tions that result in entry to test mode has been deprecated [see 8.1.1 e), 8.8.1 h), B.8.11.3 d), and
B.8.11.3 e )].
— To increase the flexibility with which instructions may be implemented and merged, the implicitly
merged SAMPLE/PRELOAD instruction has been redefined as two separate instructions: SAMPLE
and PRELOAD. These instructions can continue to share a single binary code, effectively resulting
in a merged SAMPLE/PRELOAD instruction, but alternatively, they may now share binary codes
with other instructions, provided that no rules for any of the merged instructions are violated. [see
8.1.1 g), 8.2.1 b), 8.6, 8.7, B.5.1.2, B.6.3 b), B.8.11.3 f), B.8.11.3 g), B.8.11.3 h), B.8.11.3 i),
B.8.11.3 j), and B.8.13.3 a)].
— To enable more efficient implementation of boundary-scan register cells provided at system logic
outputs, the source of data to be captured in such cells in response to the SAMPLE instruction is
now allowed to be at the connected system pin [see 8.6.1 d), 11.6.1 a), 11.6.1 b), B.8.14.4 l), and
B.10.2.4.1 b)]. Additionally, three new cell types based on this implementation (BC_8, BC_9, and
BC_10) have been added to the Standard VHDL Package (see B.5.1.2, B.9, and Table B.3).
— To permit more flexible boundary-scan register cell implementations, sharing of circuitry between
the boundary-scan register and other elements of the test and/or system logic has been allowed in
limited cases [see 11.2.1 j) and 11.2.1 k)].
— To support more complete description of IC pin drivers with bus keeper circuits, a new value for
<disable result> has been defined (KEEPER, see B.5.1.2, B.8.14.1, and B.8.14.3.7).
— To track the widespread acceptance of BSDL, the language has been made a normative part of the
standard and its use for documentation has been mandated (see 13.3.1 c) and Annex B).
Additionally, a number of minor changes were made to correct and clarify the language of the standard [of
special note, see 4.8.1 c), 11.7.1 b), B.8.14.4 k), and B.8.14.4 n)].
Participants
At the time of the issue of IEEE Std 1149.1-2001, the members of the working group were:
Christopher J. Clark, Chair
Adam W. Ley, Editor
John Andrews
Bill Aronson
Carl F. Barnhart
Dilip K. Bhavsar
Terry Borroz
John Braden
Bill Bruce
Tapan J. Chakraborty
Sung Chung
Jim Coleman
Frans De Jong
Bulent Dervisoglu
Ted Eaton
Bill Eklow
Dean Geerdes
Grady L. Giles
Peter Hansen
Neil Jacobson
Najmi Jarwala
London Jin
Wuudiann Ke
Arthur Khu
Ramesh Krishnamurthy
Tom Langford
Larry Lee
Colin Maunder
Benoit Nadeau-Dostie
Jay Nejedlo
Kenneth P. Parker
Michael Ricchetti
Gordon D. Robinson
Robert J. Russell
Adam Sheppard
Steve Stark
Ron Walther
Lee Whetsel
Thomas W. Williams
Copyright © 2001 IEEE. All rights reserved. v
The following members of the balloting group voted on this standard. Balloters may have voted for
approval, disapproval, or abstention. :
When the IEEE-SA Standards Board approved this standard on 14 June 2001, it had the following
membership:
Donald N. Heirman, Chair
James T. Carlo, Vice Chair
Judith Gorman, Secretary
*Member Emeritus
Also included are the following nonvoting IEEE-SA Standards Board liaison:
Alan Cookson, NIST Representative
Donald R. Volzka, TAB Representative
Don Messina
IEEE Standards Project Editor
John Andrews
Carl Barnhart
Roger Bennetts
Terry Borroz
John Braden
Keith Chow
Sung S. Chung
Chris J. Clark
Frans de Jong
Ted Eaton
William Eklow
Dean Geerdes
Grady Giles
Peter Hansen
Lee F. Horney
Mitsuaki Ishikawa
Neil Jacobson
Jake Karrfalt
Thomas L. Langford
Adam W. Ley
Gregory A. Maston
Colin Maunder
Patrick McHugh
Earl J. Meiers
Yinghua Min
James A. Monzel
Benoit Nadeau-Dostie
Jay Nejedlo
Bruce E. Peterson
Mike Ricchetti
Gordon Robinson
Jaideep Roy
Robert J. Russell
Scott A. Yalcourt
T. W. Williams
Satish K. Aggarwal
Mark D. Bowman
Gary R. Engmann
Harold E. Epstein
H. Landis Floyd
Jay Forster*
Howard M. Frazier
Ruben D. Garzon
James H. Gurney
Richard J. Holleman
Lowell G. Johnson
Robert J. Kennelly
Joseph L. Koepfinger*
Peter H. Lips
L. Bruce McClung
Daleep C. Mohla
James W. Moore
Robert F. Munzner
Ronald C. Petersen
Gerald H. Peterson
John B. Posey
Gary S. Robinson
Akio Tojo
Donald W. Zipse
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