IEEE1149.1测试标准资源-CSDN文库

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### IEEE1149.1测试标准：Altera FPGA中的应用 #### 一、引言与背景随着印刷电路板（Printed Circuit Board, PCB）技术的快速发展，电路板日益复杂化，对测试的需求变得尤为重要。传统的测试方法，如外部探针测试或“钉床”测试装置等，在面对越来越紧凑的PCB时显得越来越难以实施。因此，虽然缩小PCB空间可以降低成本，但同时也增加了传统测试方法的成本。为了解决这一问题，1980年代，由多个公司组成的联合测试行动小组（Joint Test Action Group, JTAG）开发了一种边界扫描测试（Boundary-Scan Testing, BST）规格，并最终将其标准化为IEEE Std. 1149.1规范。这种测试架构能够高效地检测PCB上间距紧密的元件连接情况，无需使用物理测试探针，同时还能在设备正常运行时捕获功能数据。 #### 二、IEEE1149.1标准概述 IEEE1149.1标准定义了用于边界扫描测试的基础架构和技术，使得电子设备能够在不破坏原有封装的情况下进行内部测试和诊断。该标准主要包括以下几个方面： 1. **BST架构**：边界扫描测试的基本架构包括串行数据输入（Serial Data In, SDI）、边界扫描单元（Boundary-Scan Cell）、核心逻辑（Core Logic）和串行数据输出（Serial Data Out, SDO）。通过这些组件，可以在没有物理接触的情况下实现信号的强制输入和数据的捕获。 2. **边界扫描寄存器**：每个边界扫描单元都包含一个边界扫描寄存器，用以存储和传递测试数据。测试数据被串行地移入这些寄存器，而捕获的数据则被串行地移出进行外部比较。 3. **操作控制**：IEEE1149.1标准还定义了一系列控制信号，用于控制测试流程，例如启动测试、移位数据等。 4. **电压支持**：考虑到不同设备可能具有不同的电源电压范围，标准还规定了如何确保在JTAG链中所有设备之间的电压兼容性。 5. **BST电路利用**：包括如何在设计中充分利用BST电路以及在某些情况下如何禁用这些电路。 6. **BST指导原则**：为了确保BST的有效性和可靠性，标准中还提供了一些设计指南。 7. **边界扫描描述语言（BSDL）支持**：这是一种用于描述边界扫描测试特性的特殊语言，有助于自动化的测试脚本编写和执行。 #### 三、Altera FPGA中的IEEE1149.1应用 Altera公司的Arria GX系列FPGA采用了IEEE1149.1标准来进行边界扫描测试。该章节主要介绍了如何在Arria GX系列设备中使用IEEE1149.1 BST电路，包括以下几点： 1. **BST架构**：详细介绍IEEE1149.1 BST的基本架构及其在Arria GX设备中的具体实现方式。 2. **边界扫描寄存器**：解释边界扫描寄存器的功能和作用，并提供具体的使用案例。 3. **操作控制**：介绍如何通过控制信号来管理和控制BST测试流程。 4. **电压支持**：讨论在JTAG链中如何处理不同的电源电压，并确保所有设备间的兼容性。 5. **BST电路利用**：探讨如何最大化利用BST电路以提高测试效率。 6. **BST电路禁用**：说明在不需要BST功能时如何安全地禁用这些电路。 7. **BST指导原则**：提供一系列设计建议，以确保BST电路在实际应用中的有效性和可靠性。此外，除了BST外，还可以使用IEEE1149.1控制器来进行Arria GX设备的在电路重配置（In-Circuit Reconfiguration, ICR），但这部分内容不在本章讨论范围内。 #### 四、结论 IEEE1149.1标准为复杂的PCB提供了有效的测试解决方案，特别是对于Altera的Arria GX系列FPGA来说，它不仅简化了测试过程，而且还提高了测试的准确性和效率。通过深入理解该标准并合理应用，可以显著提升产品的可靠性和市场竞争力。

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Altera Corporation 13–1

May 2008

13. IEEE 1149.1 (JTAG)

Boundary-Scan Testing for

Arria GX Devices

Introduction

As printed circuit boards (PCBs) become more complex, the need for

thorough testing becomes increasingly important. Advances in

surface-mount packaging and PCB manufacturing have resulted in

smaller boards, making traditional test methods (such as; external test

probes and “bed-of-nails” test fixture) harder to implement. As a result,

cost savings from PCB space reductions increases the cost for traditional

testing methods.

In the 1980s, the Joint Test Action Group (JTAG) developed a specification

for boundary-scan testing that was later standardized as the IEEE Std.

1149.1 specification. This Boundary-Scan Test (BST) architecture offers the

capability to test efficiently components on PCBs with tight lead spacing.

This BST architecture tests pin connections without using physical test

probes and captures functional data while a device is operating normally.

Boundary-scan cells in a device can force signals onto pins or capture data

from pin or logic array signals. Forced test data is serially shifted into the

boundary-scan cells. Captured data is serially shifted out and externally

compared to expected results. Figure 13–1 illustrates the concept of BST.

Figure 13–1. IEEE Std. 1149.1 Boundary-Scan Testing

Core

Logic

Serial

Data In

Boundary-Scan Cell

Core

Logic

Serial

Data Out

JTAG Device 1 JTAG Device 2

Pin Signal

Tested

Connection

AGX52013-1.2

13–2 Altera Corporation

Arria GX Device Handbook, Volume 2 May 2008

Introduction

This chapter discusses how to use the IEEE Std. 1149.1 BST circuitry in

Arria

™

GX devices, including:

■ IEEE Std. 1149.1 BST architecture

■ IEEE Std. 1149.1 boundary-scan register

■ IEEE Std. 1149.1 BST operation control

■ I/O Voltage Support in JTAG Chain

■ IEEE Std. 1149.1 BST circuitry utilization

■ IEEE Std. 1149.1 BST circuitry disabling

■ IEEE Std. 1149.1 BST guidelines

■ Boundary-Scan Description Language (BSDL) support

In addition to BST, you can use the IEEE Std. 1149.1 controller for

Arria GX device in-circuit reconfiguration (ICR). However, this chapter

only discusses the BST feature of the IEEE Std. 1149.1 circuitry.

f For information on configuring Arria GX devices via the IEEE Std. 1149.1

circuitry, refer to the Configuring Arria GX Devices chapter in volume 2 of

the Arria GX Device Handbook.

1 When configuring via JTAG make sure that Arria GX, Stratix II,

Stratix II GX, Stratix

, Cyclone

II, and Cyclone devices are

within the first 17 devices in a JTAG chain. All of these devices

have the same JTAG controller. If any of the Arria GX, Stratix II,

Stratix II GX, Stratix, Cyclone II, and Cyclone devices are in the

18th or further position, configuration fails. This does not affect

SignalTap

II or boundary-scan testing.

This chapter contains the following sections:

■ “IEEE Std. 1149.1 BST Architecture” on page 13–3

■ “IEEE Std. 1149.1 Boundary-Scan Register” on page 13–4

■ “IEEE Std. 1149.1 BST Operation Control” on page 13–7

■ “I/O Voltage Support in JTAG Chain” on page 13–17

■ “Using IEEE Std. 1149.1 BST Circuitry” on page 13–19

■ “BST for Configured Devices” on page 13–19

■ “Disabling IEEE Std. 1149.1 BST Circuitry” on page 13–20

■ “Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing” on

page 13–20

■ “Boundary-Scan Description Language (BSDL) Support” on

page 13–21

■ “Conclusion” on page 13–22

Altera Corporation 13–3

May 2008 Arria GX Device Handbook, Volume 2

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices

IEEE Std. 1149.1

BST Architecture

An Arria GX device operating in IEEE Std. 1149.1 BST mode uses four

required pins, TDI, TDO, TMS, and TCK, and one optional pin, TRST. The

TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and

TRST pins have weak internal pull-ups. The TDO output pin is powered

by V

CCIO

in I/O bank 4. All of the JTAG input pins are powered by the 3.3-

V V

CCPD

supply. All user I/O pins are tri-stated during JTAG

configuration.

1 For recommendations on how to connect a JTAG chain with

multiple voltages across the devices in the chain, refer to “I/O

Voltage Support in JTAG Chain” on page 13–17.

Table 13–1 summarizes the functions of each of these pins.

The IEEE Std. 1149.1 BST circuitry requires the following registers:

■ The instruction register determines the action to be performed and

the data register to be accessed.

■ The bypass register is a 1-bit-long data register that provides a

minimum-length serial path between TDI and TDO.

■ The boundary-scan register is a shift register composed of all the

boundary-scan cells of the device.

Table 13–1. IEEE Std. 1149.1 Pin Descriptions

Pin Description Function

TDI

Test data input Serial input pin for instructions as well as test and programming data.

Data is shifted in on the rising edge of

TCK.

TDO

Test data output Serial data output pin for instructions as well as test and programming

data. Data is shifted out on the falling edge of

TCK. The pin is tri-stated

if data is not being shifted out of the device.

TMS

Test mode select Input pin that provides the control signal to determine the transitions of

the Test Access Port (TAP) controller state machine. Transitions within

the state machine occur at the rising edge of

TCK. Therefore, TMS

must be set up before the rising edge of

TCK. TMS is evaluated on the

rising edge of

TCK.

TCK

Test clock input The clock input to the BST circuitry. Some operations occur at the

rising edge, while others occur at the falling edge.

TRST

Test reset input

(optional)

Active-low input to asynchronously reset the boundary-scan circuit.

This pin should be driven low when not in boundary-scan operation

and for non-JTAG users the pin should be permanently tied to GND.

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