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System-on-a-Chip——Design and Test.Rochit Rajsuman 评分

SOC芯片从设计到测试得所有环节,本书都覆盖到了,一本SOC设计、验证、测试得权威参考手册,无论是芯片工程师还是硬件工程师都值得一读。
For a listing of related titles from Artech house turn to the back of this book System-on-a-Chip: Design and Test Rochit Rajsuman A Artech house Boston· London www.artechhouse.com Library of Congress Cataloging-in-Publication Data ajsuman, Rochet System-on-a-chip design and test/ Rochit rajsuman cm (Artech House signal processing library) Includes bibliographical references and index ISBN 1-58053-107-5(alk. Paper) 1. Embedded computer systems-Design and construction. 2. Embedded computer systems--Testing. 3. Application specific integrated circuits- and construction. I. Title. II. Series TK7895E42R372000 621.395—dc21 00-030613 CIP British Library Cataloguing in Publication Data Rajsuinan, Rochet. Sy chip design and test. -(Artech Hou al 1. Application specific integrated circuits- Design and construction I. Title 621.395 ISBN Cover design by by Gary ragaglia C 2000 Advantest America R&D Center, Inc 3201 Scott Boulevard Santa Clara, CA 95054 All rights reserved. Printed and bound in the United States of America. No part of this book may be reproduced or utilized in any form or by any means, electronic or mechanical, in- cluding photocopying, recording, or by any in formation storage and retrieval system, with out permission in writing from the publisher All terms mentioned in this book that are known to be trademarks or service marks have been appropriately capitalized. Artech House cannot attest to the accuracy of this informa tion. Use of a term in this book should not be regarded as affecting the validity of any trade mark or service mark International Standard Book Number: 1-58053-107-5 Library of Congress Catalog Card Number: 00-030613 10987654321 Contents Preface Acknowledgment X41 Part I: Design Introduction 1.1 rchitecture of the Present-Day SoC 1.2 Design iss 1.3 Hardware-Software Codesign 1.3. 1 Codesign Flo 15 1.3.2 Codesign Tools 18 1. 4 Core Libraries, EDA Tools, and Web pointers 21 1. 4.1 Core libraries 21 1. 4.2 EDA Tools and vendors 23 1.±.3 Web pointers Refer rences Design Methodology for logic cores SoC Design Flow 2.2 General guidelines for Design reuse System-on-a-Chip: Design and Tes 2.2.1 Synchronous Design 36 2.2.2 Memory and Mixed-Signal design 36 2.2.3 On-Chip bus 2.2.4 Clock Distribution 39 2.2.5 Clear/Set/Reset Signals 40 2.2.6 Physical D 40 2.2.7 Deliverable models 42 Design Process for Soft and Firm Cores 2.3. 1 Design Flow 2.3.2 Development Process for Soft/Firm Cores 45 2.3.3 RTL Guidelines 46 2.3.4 Soft/Firm Cores Productization 47 2.4 Design process for hard cores 47 2.4.1 Uniquc Dcsign Issucs in Hard Corcs 47 2.4.2 Development Process for Hard Cores 19 2.5 gn-Off Checklist and deliverables 51 2.5.1 Sign-Off Checklist 51 2.5.2 Soft Core Deliverables 2.5.3 Hard Core deliverables 2.6 ystem integration 2.6.1 Designing With Hard Cores 53 2.6.2 Designing With Soft cores 54 2.6.3 System Verification 54 References Design Methodology for Memory and Analog cores 57 Why Large Embedded Me emories 57 Design Methodology for Embedded Memories 59 3.2. 1 Circuit Techniques 61 compile 3.2.3 Simulation models 70 pecifications of Analog Circuits 3.3.1 Analog-to-Digital Converter 3.3.2 Digital-to-Analog Converter 3.3.3. Phase-Locked Loops 78 Contents 3.4 High-Speed Circu 79 3.4.1 Rambus asic cell 79 3.4.2 IEEE 1394 Serial Bus(Firewire) PHY Layer 80 3.4.3 High-Speed I/C References 81 4 Design validation 4.1 Core-Level validation 86 4.1.1 Core validation plan 86 4.1.2 Testbench 4. 1.3 Core-Level Timing verification 90 4.2 Core Interface verification 93 4.2.1Pr I verifi 94 4.2.2 Gate-Level Simulation 4.3 SoC Design Validation 4.3.1 Cosimulation 4.3.2 Emulation 4.3.3 Hardware Prototypes 101 Re 103 Core and soc design examples 105 Microprocessor Cores 105 5.1.1 V8OR/AV Superscaler RiSC Core 109 5.1.2 Design of PowerPC 603e G2 Core 110 5.2 Comments on memory core generators 112 Core Integration and on-Chip bus 5.4 Examples of SoC 115 5.4.1 Media processors 116 5.4.2 Testability of Set-Top Box SoC 121 References 122 Part l test 123 Testing of Digital Logic cores 6.1 Soc test i 126 System-on-a-Chip: Design and Tes 1 and isolation 128 6.3 IEEE P1500 Effort 129 6.3. 1 Cores Without Boundary Scan 6.3.2 Core Test language 135 6.3.3 Cores With Boundary Scan 135 6.4 Corc te 138 6.5 Test Methodology for Design Reuse 142 6.5.1 Guidelines for Core ' Testability 142 6.5.2 High est Synthes 6.6 Testing of Microprocessor Cores 144 6.6.1 Built-in Self-Test Method 144 6.6.2 Example: Testability Features of ARM Processor Core 147 6.6. 3 Debug Support for Microprocessor Cores 150 Referenc 152 Testing of Embedded Memories 155 7.1 Memory Fault Models and Test Algorithms 156 7. 1.1 Fault Modcls 156 7. 1. 2 Test algorithms 157 7.1.3 Effectiveness of Test Algorithms 160 7.1.4 Modification With Multiple Data Background 161 7. 1.5 Modification for Multiport memories 161 7.1.6 Algorithm for Double-Buffered Memories 161 7.2 Test methods for embedded memories 162 7. 2. 1 Testing Through ASIC Functional Test 163 7. 2.2 Tcst Appl 164 7. 2. 3 Test applic Collar regi 16④ 7.2.4 Memory Built-in Self-Test 164 7.2.5 Testing by On-Chip Microprocessor 169 7.2.6 Summary of Test Methods for embedded memories 171 7.3 Memory redundancy and repair 171 7.3.1 Hard Re 7.3.2 Soft ro 175 7.4 Error Detection and Correction Codes 175 Contents 5 Production Testing of SoC With Large Embedded Memory 176 177 Testing of Analog and Mixed-signal Cores 1 8.I Analog parameters and Characterization 182 8.1.1 Digital-to-Analog Converter 182 8.1.2 Analog-to-Digital Converter 184 8. 1. 3 Phase-Locked L 188 8.2 Design-for-Test and Built-in Self-Test methods for Analog cores 191 8. 2.1 Fluence Technologys Analog BIST 192 8.2.2 Logicvision's Analog 192 8.2.3 Testing by On-Chip Microprocessor 195 8.24 IEEE P1149,4 197 8.3 Testing of Specific Analog Circuits 200 8.3. 1 Rambus ASIC Cell 200 8.3.2 Testing of 1394 Serial Bus/Firewire 201 erences ddq Testing 207 9.1 Physical Defects 207 9.1.1 Bridging(Shorts) 208 9.1.2 Gate-Oxide Defe 212 9.1.4 Effectiveness of Iddq testing 9.2 g Difficu 218 9.3 Design-for-Iddq-Testing 224 9.4 Design Rules for Iddq testing 228 9.5 Iddq Test Vector Generation 230 Re eferences 234 10 Production Testing 239 10.1 Production Test flow 239

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