非常全面的ADT7316 ADT7317 ADT7318温度传感器资料，可以作为参考。
ADT7316/ADT7317/ADT7318 SPECIFICATIONS Table 1. Temperature ranges are as follows: A Version: -400C to +120@. vDd=2. 7 V to 5.5 V, GND=0V, REFIN=2.25 V, unless otherwise noted Parameter Min Typ Max Unit Conditions/Comments DAC DC PERFORMANCE2, adT318 Resolution Bits Relative Accuracy ±0.15±1 LSB Differential Nonlinearity ±0.02±0.25 LSB Guaranteed monotonic over all codes ADT7317 Resolution Bits Relative Accuracy ±0.5±4 LSB Differential nonlinearity ±0.05±0.5 LSB Guaranteed monotonic over all codes ADT7316 Resolution Bits ative Accuracy ±16 LSB Differential Nonlinearity ±0.02±0.9 LSB Guaranteed monotonic over all codes offset error ±04±2 %o of esr Gain error ±04±2 do of fsr Lower dead band Lower dead band exists only if offset error is negative. See Upper Dead Band 100 Upper dead band exists if VREf= vou and offset plus gain error is positive. See Figure 3 Offset Error drift ppm or FSR/°C Gain error drift ppm of FSR°C DC Power Supply Rejection Ratio 60 dB △VD=±10% DC Crosstalk 200 See figure 6 THERMAL CHARACTERISTICS Internal reference used. Averaging on INTERNAL TEMPERATURE SENSOR Accuracy at Vod=3.3V+10% ±1.5 TA=85C ±0.5±3 TA=0°Cto+85°C ±5 TA=-40°Cto+120°C Accuracy at VDD=5V±5% ±2 ℃℃℃o℃io℃℃o TA=0°Cto+85°C ±3 ±5 TA=-40°Cto+120°C. Resolution 10 its Equivalent to025°C Long term Drift 0.25 Drift over 10 years if part is operated at 55C EXTERNAL TEMPERATURE SENSOR External Transistor= 2N3906 Accuracy at VDD=3.3V+10% ±15 TA=85°C ±3 TA=0°Cto+85°C. TA=-40°Cto+120°C. Accuracy at v=5V±5% ±2 3 TA=0°Cto+85°C. TA=-40°Cto+120°C Resolution 10 ts Equivalent to0.25℃ Output source current 180 A High level A Low level Thermal Voltage Output 8-Bit DAC Output Resolution Scale fact 8.79 °C oV to vε Output.TA=-40°Cto+120C 17.58 V°C 0Vto2 VREF Output.TA=-40°Cto+120°C. See Terminology 2DC specifications tested with the outputs unloaded LInearity is tested using a reduced code range: ADt7316 ( code 115 to 4095); ADt7317(code 28 to 1023): ADT7318(code 8 to 255) Rev. A Page 3 of 40 ADT7316/ADT7317/ADT7318 Parameter Min Typ Max Unit Conditions/Comments 10-Bit DAC Output Resolution 0.25 Scale factor 2.2 mV/°C 0 to VREF Output.TA=-40℃Cto+120°C 4.39 mV/°C 0vto2 VREF Output.TA=-40°Cto+120°C CONVERSION TIMES Single Channel Mode Slow adc Averaging(16 samples)on 712 Averaging off Internal Temperature 114 Averaging(16 samples)on 712 eraging f External Temperature 24.22 ms Averaging(16 samples)on 1.51 ms Averaging off Fast ADc Averaging(16 samples)on 44.5 Averaging off Internal Temperature 2.14 ms Averaging(16 samples)on 134 Averaging off External Temperature 14.25 ms Averaging(16 samples)on 890 Averaging off ROUND ROBIN UPDATE RATE Time to complete one measurement cycle through all channels S| OW ADC at25°C Averaging On 5995 ms Averaging Off 652 ms Fast adc at 25C Averaging on 1959 Averaging off 289 ms DAC EXTERNAL REFERENCE INPUTS VREF Input range Buffered reference mode VAFF Input range 0.25 Un buffered reference mode VREF Input Impedance 37 45 kQ Unbuffered reference mode oV to 2 VREF output kQ Unbuffered reference mode o V to VREr output rang 10 MQ Buffered reference mode and power-down mode Ret 10 kHz Channel-to-Channel isolation -75 dB Frequency =10 kHz. ON-CHIP REFERENCE Reference Voltage 2 Temperature Coefficient 80 ppm/c OUTPUT CHARACTERISTICSS Output Voltage 0.001 Voot This is a measure of the minimum and maximum drive 0.001 capability of the output amplifier DC Output Impedance 0.5 Short circuit current A VoD=5V 16 A 3V. Power-Up Time 2.5 Coming out of power-down mode. VDD=5V. Coming out of power-down mode. VDD=3.3 V. Round robin is the continuous sequential measurement of the following three channels: VoD, internal temperature, and external temperature Guaranteed by design and characterization, but not production tested 6In order for the amplifier output to reach its minimum voltage the offset error must be negative In order for the amplifier output to reach its maximum voltage, VRof VcD, offset plus gain error must be positive Rev. A Page 4 of 40 ADT7316/ADT7317/ADT7318 Parameter MinTyp Max UnitConditions/Comments DIGITAL INPUTS Input Current Vin=oV to vdp. Input Low Voltage, vil 08 Input High Voltage, VIH 1.89 Pin Capacitance all digital inputs SCL, SDA Glitch Rejection Input filtering suppresses noise spikes of less than 50 ns LDAC Pulse Width 0 Edge triggered input DIGITAL OUTPUT Output High voltage, VoH 24 RCE=ISINK=200 HA. Output Low Voltage, VoL 04 V lol=3 mA Output High Current, IoH mA VOH=5V Output Capacitance, CoU NTANT Output Saturation Voltage 08 V louT= 4 mA FC TIMING CHARACTERISTICS,8 Serial Clock period, tu 2.5 Fast-mode lC. See Figure 4 Data In Setup Time to SCL High, tz Data Out Stable after SCL Low t3 See Figure 4 SDA LoW Setup Time to SCL Low(Start 50 See Figure 4 Condition) ta SDA High Hold Time after SCL High ns See Figure 4 (Stop Condition),ts SDA and SCL Fall Time te ns See Figure 4 SPI TIMING CHARACTERISTICS, 1O Sto SCLK Setup Time, tr See Figure 7. SCLK High Pulse Width, t2 ns See Figure 7 SCLK Low Pulse, t3 ns See Figure 7. Data Access Time after SCLK Falling 35 ns See figure 7 Edge, t4' Data Setup Time Prior to SCLK Rising20 See Figure 7 Edge, t; Data Hold Time after SCLK Rising 0 ns See Figure 7 Edge, to CSto SCLK Hold Time, t/ See Figure 7 CSto dout high Impedance, ts See Figure 7 POWER REQUIREMENTS 2.7 5.5 VoD Settling time VoD settles to within 10% of its final voltage level Inn(normal Mode 2 Vod=33V VH= Vop and VI= gnd A VDp=5V, VH= VoD and VI=GND pp(Power Down Mode 10 A Vop=3.3V, VH= Vpp and VL= GND A Vdd=5V, VH= Vop and VIl= gnD. Power Dissipation VDD=3.3 V Using Normal Mode. 33 VDD=3.3 V Using Shutdown Mode The sDa and scl timing is measured with the input filters turned on so as to meet the fast-mode 2c specification Switching off the input filters improves the transfer rate but has a negative effect on the EMc behavior of the part gUaranteed by design. Not tested in production gUaranteed by design and characterization, but not production tested 10 All input signals are specified with tr=tf=5 ns(10% to 90% of Voo)and timed from a voltage level of 1.6V MEasured with the load circuit of figure 5 lDD specification is valid for all DAC codes. Interface inactive. All DACs active Load currents excluded Rev. A Page 5 ADT7316/ADT7317/ADT7318 GAIN ERROR SCL OFFSET ERROR t5 LTA DATA IN SDA DATA OUT NEGATIVE Figure 4. FC Bus Timing Diagram OFFSET DAC CODE ERROR ACTUAL -- DEAL LOWER DEADBAND CODES AMPLIFIER TO OUTPUT FOOTROOM 1.6v NEGATIVE OFFSET 200uA ERROR Figure 5. Load Circuit for Access Time and Bus Relinquish Time Figure 2. DAC Transfer Function with Negative Offset GAIN ERROR y OFFSET ERROR UPPER 24.7kQ R DEADBAND CODES TO DAC UTPUT 4.7kG 200pF ACTUAL 〓== IDEAL igure 6. Load Circuit for DAC Outputs E eRROR DAC CODE FULLSCALE Figure 3. DAC Transfer Function with Positive Offset(VREF=Vo t1 SCLK 子一 DIN D7 D6 D5 DO X X DOUT xxXx× XXXxXxXxxxxr(-Xmxm吗x四xXm Figure 7. SP/ Bus Timing Diagram Rev. A Page 6 of 40 ADT7316/ADT7317/ADT7318 FUNCTIONAL BLOCK DIAGRAM ADDRESS POINTER INTERNAL TEMPERATURE REGISTER TEMPERATURE VALUE REGISTER STRING REGISTERS REGISTERS ANALOG VALDE REGISTERS DAC B COMPARATOR REGISTERS REGISTERS CONTROL CONFIG. 1 EXTERNAL TEMPERATURET DAC C SENSOR VALUE REGISTER REGISTERS DAC C (Vour-C CON REGI STENFIG 2 CONTROL CONFIG REGISTERS ADT7316/ ATION ADT7317 ADT7318 SELECT LDAC CONFIGURATION L。G|c REGISTER STATUS NTERRUPT MASK REGISTERS 10)INT/INT REGISTERS SMBus/SPI INTERFACE REFERENCE GND CS SCLSCLK SDA/DIN DOUTIADD LDAC VREF-AI Figure 8. Rev. A Page 7 of 40 ADT7316/ADT7317/ADT7318 DAC AC CHARACTERISTICS Table 2. Guaranteed by design and characterization, but not production tested VDD=2.7 V to 5.5 V; Rl=4.7 kQ2 to GnD; CL= 200 pF to GND; 4.7 kn to VDD. All specifications tmiN to TMAx, unless otherwise noted. Parameter Min Typ(@ 25C) Max Unit Conditions and Comments Output Voltage Settling Time VREF= VoD=+5 V ADT73 18 1/4 scale to 3 4 scale change (0x40 to OxcO ADT7317 678 s 1/4 scale to 3 /4 scale change(0x100 to Ox300) ADT7316 10 1/4 scale to 3 /4 scale change(0X400 to OXCOo Slew rate 0.7 ∨|us Major-Code Change glitch Energy 12 nv-s 1 LSB change around major carry Digital Feedthrough 0.5 Digital Crosstalk nV-s Analog Crosstalk 0.5 nv-s DAO-to-DAC Crosstalk V-s Multiplying bandwidth 200 kHz VREI=2V±01Vpp Total Harmonic Distortion 70 dB VREF=2.5V+0.1V p-p Frequency= 10 kHz. See terminology section Rev. A Page 8 of 40 ADT7316/ADT7317/ADT7318 ABSOLUTE MAXIMUM RATINGS Table 3 Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Vcp to GNd 0.3V to +7v ng only ly; functional operation of the device at these or any Digital Input Voltage to GND 0.3 V to Vp+0.3∨ other conditions above those indicated in the operational Digital Output Voltage to GND 0.3V to VDp+0.3 V section of this specification is not implied. Exposure to absolute Reference Input Voltage to GND 0.3 V to VDp+0.3 V maximum rating conditions for extended periods may affect Operating Temperature range 40°cto+120°C device reliabili Storage temperature range 65°cto+150°C Junction Temperature 150°C 16-Lead QSoP Package Table 4. iC Address selection Power Dissipation (T, max-TA)/0JA ADD Pin 12C Address Thermal Impedance 1001000 eIA Junction-to-Ambient 10544°C/W Float 1001010 eic Junction-to-Case 388°C/W High 1001011 IR Reflow Soldering Peak Temperature 220C(0/5℃C Time at Peak Temperature 10 sec to 20 sec Ramp-Up Rate 2°C/ sec to3°C/seC Ramp-Down Rate 6°C/seC Values relate to package being used on a 4-layer board Junction-to-case resistance is applicable to components featuring a preferential flow direction, e.g., components mounted on a heat sink Junction - to-ambient resistance is more useful for air-cooled PcB-mounted components ESD CAUTION ESD(electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection although this product features WARNING! proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance ESD SENSITIVE DEVICE degradation or loss of functionality Rev. A Page 9 of 40 ADT7316/ADT7317/ADT7318 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOUT B1. ADT7316/ VREF-AB B ADT7317/14]VREF-CD ADT7318 3]ScL/SCLK GN (Not to Scale) 10INT/INT Figure 9 Pin Configuration QSOP Table 5. adt7316/ Adt7317/ADT7318 Pin Function Descriptions Pin Mnemonic Description No Buffered Analog output Voltage from DAC B The output amplifier has rail-to-rail operation VOUT-A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation Reference Input Pin for DACs a and B. It may be configured as a buffered or unbuffered input to both dACs a and B. It has an input range from 0. 25v to VoD in unbuffered mode and from 1 v to voD in buffered mode DACs a and b default is pIn SPl Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables the input register and data is transferred in on the rising edges and out on the falling edges of the subsequent serial clocks. It is recommended that this pin be tied high to Von when operating the serial interface in 2C mode GND Ground Reference Point for All Circuitry on the Part. Analog and digital ground Positive Supply voltage, 2.7V to 5.5 V The supply should be decoupled to ground D+ Positive connection to external temperature sensor 8 Negative connection to external temperature sensor. 9 LDAC Active low control input that transfers the contents of the input registers to their respective dAC registers a falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. a minimum pulse idth of 20 ns must be applied to the Ldac pin to ensure proper loading of a dac register This allows simul update of all DAC outputs. Bit C3 of Control Configuration 3 register enables LDac pin Default is with LdAc pin controlling the loading of DAC registers 10INT/INT Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when temperature or VpD limits are exceeded. Default is active low Open-drain output-needs a pull-up resistor DOUT/ADD SPL, Serial Data Output Logic output Data is clocked out of any register at this pin. Data is clocked out on the falling edge of SCLK Open-drain output--needs a pull-up resistor ADD, 2C Serial Bus Address Selection Pin Logic input. a low on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. the 1c address set up by the add pin is not latched by the device until after this address has been sent twice. On the eighth SCl cycle of the second valid communication, the serial bus address is latched in. Any subsequent changes on this pin will have no affect on the pc serial bus address 12 SDA/DIN SDA, 12C Serial Data Input. I2C serial data that is loaded into the devices registers is provided on this input Open-drain configuration -needs a pull-up resistor. DIN, SPI Serial Data Input Serial data to be loaded into the device's registers is provided on this input Data is clocked into a register on the rising edge of sCLK open-drain configuration -needs a pull-up resistor 13 SCL/SCLK Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any registerof the adt7316/ADT731 7/ADt731 8 and also to clock data into any register that can be written to Open-drain configuration--needs a pull-up resistor 14 VREF-CD Reference Input pin for dacs c and d. It may be configured as a buffered or unbuffered input to both dacs c and d. It has an input range from 0. 25 v to vod in unbuffered mode and from 1 v to Vod in buffered mode. DAcs c and d default on power-up, to this pin 15VOUT-D Buffered Analog output voltage from DAC D The output amplifier has rail-to-rail operation 16 VOUT-C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation Rev. A Page 10 of 40