uart接收_VHDL程序.rar

entity OPB_UARTLITE_RX is port ( Clk : in std_logic; Reset : in std_logic; EN_16x_Baud : in std_logic; Use_Parity : in std_logic; Odd_Parity : in std_logic; RX : in std_logic; Read_RX_FIFO : in std_logic; Reset_RX_FIFO : in std_logic; FIFO_Triger : in std_logic_vector(6 downto 0); Match_Trige : out std_logic; RX_Data : out std_logic_vector(7 downto 0); --(0 to C_DATA_BITS-1) RX_Data_Present : out std_logic; RX_BUFFER_FULL : out std_logic; RX_Frame_Error : out std_logic; RX_Overrun_Error : out std_logic; RX_Parity_Error : out std_logic );