DEI1016芯片数据手册资源-CSDN文库

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·两个接收器和一个发射器 ·销钉更换部件的行业标准销钉 ·全包自检模式 ·字长可配置为25位或32位操作 ·奇偶性接收和传输词的状态和生成 ·8个字发送缓冲器 ·低功耗CMOS ·支持多种ARINC协议:429、571、575、706 ·可提供扩展(-55/+85°C)和军用(-55/+125°C)温度范围 ·可提供QFP、PLCC、LCC和CDIP包 DEI1016是一款专为航空电子领域设计的串行数字数据总线与16位宽数字数据总线之间接口的芯片。该芯片具备两个接收器和一个发射器，可实现灵活的数据处理。它的主要特点包括： 1. **接收器与发射器**：DEI1016包含两个独立的接收通道，每个通道直接电气连接到ARINC数据总线，确保数据接收的稳定。同时，它有一个8X32位缓冲器的单通道发射器，允许主机将数据块写入并自动发送，无需主机计算机持续关注。 2. **字长配置**：用户可以根据需求将字长配置为25位或32位，以适应不同的应用需求。 3. **奇偶性校验**：在接收和传输过程中，DEI1016提供了奇偶性状态和生成功能，增强了数据的完整性和可靠性。 4. **全包自检模式**：芯片内置了自检模式，可以进行内部电路的完整性检测，保证了设备在运行过程中的稳定性。 5. **8字发送缓冲器**：发射器内置8字缓冲器，能有效地管理和调度待发送的数据，确保数据传输的流畅。 6. **低功耗CMOS技术**：采用低功耗CMOS工艺，使得芯片在提供高性能的同时，保持了较低的能耗，适合于电池供电或对功耗有严格限制的系统。 7. **ARINC协议支持**：DEI1016支持多种ARINC协议，包括ARINC 429、571、575和706，适用于多种航空电子通信标准。 8. **温度范围**：芯片提供了扩展温度范围(-55°C to +85°C)和军事级温度范围(-55°C to +125°C)，适应各种极端环境。 9. **封装选项**：DEI1016提供多种封装形式，包括QFP、PLCC、LCC和CDIP，以满足不同安装和空间需求。在实际应用中，DEI1016通过其控制寄存器让主机能够选择不同的操作选项。TX FIFO（传输FIFO）是8个字节宽的32位缓冲区，用于存储待发送的数据。接收解码器和发射编码器分别处理接收和发送数据，确保数据格式与ARINC 429兼容。自测数据功能则用于检测芯片自身的功能是否正常。 DEI1016是一款功能强大的ARINC协议转换器，广泛应用于航空电子系统，特别是在需要高可靠性、低功耗和多协议支持的场合。通过其丰富的特性，DEI1016能够无缝集成到基于STM32、ARM或单片机的嵌入式硬件系统中，实现串行数据的高效传输和处理。

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8/14/2020

Features

· Two Receivers and One Transmitter

· Industry Standard Pin for Pin Replacement Part

· Wraparound Self-Test mode

· Word length can be configured for 25 bit or 32 bits operation

· Parity Status and generation of Receive and Transmit Words

· 8 Word Transmitter buffer

· Low Power CMOS

· Supports multiple ARINC protocols: 429, 571, 575, 706

· Available in extended (-55/+85°C) and Military (-55/+125°C) temperature ranges

· Available in QFP, PLCC, LCC and CDIP packages

General Description:

The DEI1016 provides an interface between a standard avionics type serial digital data bus and a 16-bit-wide digital data

bus. The interface circuit consists of a single channel transmitter with an 8X32 bit buffer, two independent receive

channels, and a host programmable control register to select operating options. The two receiver channels operate

identically, each providing a direct electrical interface to an ARINC data bus.

The transmitter circuit contains an 8 word by 32 bit buffer memory and control logic which allows the host to write a block

of data into the transmitter. The block of data is transmitted automatically by enabling the transmitter with no further

attention by the host computer. Data is transmitted in TTL format on the D0(A)/D0(B) output pins. The signal format is

compatible with DEI’s extensive line of ARINC 429 Line drivers for easy connection to the ARINC data bus.

DEI1016/DEI1016A/DEI1016B

ARINC 429 Transceiver

Family

Control

TX FIFO

8 Words X 32 Bits

Receive

Decoder

Receive

Decoder

Transmit

Encoder

ARINC 429

Receive 0

ARINC 429

Receive 1

Self Test Data

ARINC 429

Transmit

DATA BUS

Host

Interface

/DR1, /DR2

TXR

/OE1, /OE2

/LD1, /LD2

ENTX

/LDCW

/DBCEN

/MR

Figure 1: DEI1016 Block Diagram

deiaz.com

8/14/2020

Table 3: DEI 1016 AC Electrical Characteristics

PARAMETER

SYMBOL

Data Rate

100kbps

Data Rate

12.5kbps

MIN MAX MIN MAX UNITS

1MCK Frequency f

1MCK

1.01 1.01 MHz

1MCK Duty Cycle CK

40 60 40 60 %

1MCK Rise/Fall Time T

CRF

10 10 ns

Master Reset Pulse Width T

200 200 ns

Transmitter Data Rate (1MCK = 1MHz) T

99 101 12.4 12.6 kbps

Receiver Data Rate (1MCK = 1MHz),(DATA = 50%

BIT/ 50% NULL TIME)

95 105 8.0 14.5 kbps

Table 4: Pin Definitions

SYMBOL DEFINITION

Power Input. +5VDC ±10%

GND Power Return and Signal Ground.

DI1(A) ARINC 429 Input. Receiver Channel 1, “A” input

DI1(B) ARINC 429 Input. Receiver Channel 1, “B” input

DI2(A) ARINC 429 Input. Receiver Channel 2, “A” input

DI2(B) ARINC 429 Input. Receiver Channel 2, “B” input

/DR1 Logic Output. Data Ready, Receiver 1. A Low output indicates valid data in receiver 1.

/DR2 Logic Output. Data Ready, Receiver 2. A Low output indicates valid data in receiver 2.

SEL Logic Input. Receiver word select. A Low input selects receiver Word 1; Hi selects Word 2 to be read on

D[15:0] port.

/OE1 Logic Input. Receiver 1 Output Enable. A Low input enables the D[15:0] port to output Receiver 1 data.

Word 1 or Word 2 will be output as determined by the SEL input.

/OE2 Logic Input. Receiver 2 Output Enable. A Low input enables the D[15:0] port to output Receiver 2 data.

Word 1 or Word 2 will be output as determined by the SEL input.

D[15:0] Logic Input / Tri-state Output. This 16-bit bi-directional data port is the uP data interface. Receiver data is

read from this port. Control Register and Transmitter FIFO data is written into this port.

/LD1 Logic Input. Load Transmitter Word 1. A Low input pulse loads Word 1 into the Transmitter FIFO from

D[15:0].

/LD2 Logic Input. Load Transmitter Word 2. A Low input pulse loads Word 2 into the Transmitter FIFO from

D[15:0].

TXR Logic Output. Transmitter Ready. A Hi output indicates the Transmitter FIFO is empty and ready to accept

new data.

DO(A) Logic Output. Transmitter serial data ‘A’ output. This is a return-to-zero format signal which will normally

feed an ARINC 429 Line Driver IC. A Hi output indicates the Transmitter data bit is a 1. The signal returns

to zero for second half of bit time.

DO(B) Logic Output. Transmitter serial data ‘B’ output. This is a return-to-zero format signal which will normally

feed an ARINC 429 Line Driver IC. A Hi output indicates the Transmitter data bit is a 0. The signal returns

to zero for second half of bit time.

ENTX Logi

c Input. Enable Transmitter. A Hi input enables the Transmitter to send data from the Transmitter FIFO.

This must be Low while writing data into Transmitter FIFO. Transmitter memory is cleared by high-to-low

transition.

/LDCW Logic Input. Load Control Register. A Low input pulse loads the Control Register from D[15:0].

1MCK Logic Input. External Clock. Master clock used by both the Receivers and Transmitter. The 1MHz rate is a

X10 clock for the HI data rate (100 kbps), and a X80 clock for LO data rate (12.5 kbps).

TXCK Logic Output. Transmitter Clock. This outputs a clock frequency equal to the transmit data rate. The clock

is always enabled and in phase with the data. The output is Hi during the first half of the data bit time.

/MR Logic Input. Master Reset. A Lo input resets the Transmitter FIFO, bit counters, word counter, gap timers,

/DRx, and TXR. The Control Register is not affected. Used on power up and system reset.

/DBCEN Logic Input with internal pull up to V

. Data Bit Control Enable. A Low input enables the transmitter parity

bit control function as defined by control register bit 4 (PAREN). A Hi input forces transmitter parity bit

insertion regardless of PAREN value. The pin is normally left open or tied to ground.

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