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SX1213 Receiver

Ultra-Low Power Integrated UHF Receiver

ADVANCED COMMUNICATIONS & SENSING

Rev.2 – July 1

, 2009 Page 1 of 65 www.semtech.com

General Description

The SX1213 is a low cost single-chip receiver

operating in the frequency ranges from 300MHz to

510MHz. The SX1213 is optimized for very low power

consumption (3mA). It incorporates a baseband

demodulator with data rates up to 200 kb/s. Data

handling features include a sixty-four byte FIFO,

packet handling, CRC and data whitening processing.

Its highly integrated architecture allows for minimum

external component count whilst maintaining design

flexibility. All major RF communication parameters are

programmable and most of them may be dynamically

set. It complies with European (ETSI EN 300-220

V2.1.1) and North American (FCC part 15.247 and

15.249) regulatory standards.

Ordering Information

Table 1: Ordering Information

Part number Delivery

Minimum Order

Quantity / Multiple

SX1213IWLTRT Tape & Reel 3000 pieces



 TQFN-32 package – Operating range [-40;+85°C]

 T refers to Lead Free packaging

 This device is WEEE and RoHS compliant

Features

 Low Rx power consumption: 3mA

 Good reception sensitivity: down to -104 dBm at

25 kb/s in FSK, -110 dBm at 2kb/s in OOK

 Packet handling feature with data whitening and

CRC processing

 RSSI (Received Signal Strength Indicator) range

from Rx noise floor to 0 dBm

 Bit rates up to 200 kb/s, NRZ coding

 On-chip frequency synthesizer

 FSK and OOK modulation

 Incoming sync word recognition

 Built-in Bit-Synchronizer for incoming data and

clock synchronization and recovery

 5 x 5 mm TQFN package

 Optimized Circuit Configuration for Low-cost

applications

 Pin to pin compatible with SX1212 Transceiver

Applications

 Wireless alarm and security systems

 Wireless sensor networks

 Automated Meter Reading

 Home and building automation

 Industrial monitoring and control

 Remote Wireless Control

Application Circuit Schematic

SX1213

ADVANCED COMMUNICATIONS & SENSING

Rev.2 – July 1

, 2009 Page 2 of 65 www.semtech.com

Table of Contents

1. General Description ................................................................... 5

1.1. Simplified Block Diagram................................................... 5

1.2. Pin Diagram ....................................................................... 6

1.3. Pin Description................................................................... 7

2. Electrical Characteristics............................................................ 8

2.1. ESD Notice ........................................................................ 8

2.2. Absolute Maximum Ratings............................................... 8

2.3. Operating Range ............................................................... 8

2.4. Chip Specification.............................................................. 8

2.4.1. Power Consumption .................................................. 8

2.4.2. Frequency Synthesis................................................. 9

2.4.3. Receiver .................................................................. 10

2.4.4. Digital Specification................................................. 11

3. Architecture Description........................................................... 12

3.1. Power Supply Strategy .................................................... 12

3.2. Frequency Synthesis Description .................................... 13

3.2.1. Reference Oscillator................................................ 13

3.2.2. CLKOUT Output ...................................................... 13

3.2.3. PLL Architecture...................................................... 14

3.2.4. PLL Tradeoffs.......................................................... 14

3.2.5. Voltage Controlled Oscillator................................... 15

3.2.6. PLL Loop Filter........................................................ 16

3.2.7. PLL Lock Detection Indicator .................................. 16

3.2.8. Frequency Calculation ............................................ 16

3.3. Receiver Description........................................................ 18

3.3.1. Architecture ............................................................. 18

3.3.2. LNA and First Mixer ................................................ 19

3.3.3. IF Gain and Second I/Q Mixer................................. 19

3.3.4. Channel Filters ........................................................ 19

3.3.5. Channel Filters Setting in FSK Mode ...................... 20

3.3.6. Channel Filters Setting in OOK Mode ..................... 21

3.3.7. RSSI ........................................................................ 21

3.3.8. Fdev Setting in Receive Mode ................................ 23

3.3.9. FSK Demodulator.................................................... 23

3.3.10. OOK Demodulator................................................. 23

3.3.11. Bit Synchronizer .................................................... 26

3.3.12. Alternative Settings ............................................... 27

3.3.13. Data Output ........................................................... 27

4. Operating Modes...................................................................... 28

4.1. Modes of Operation ......................................................... 28

4.2. Digital Pin Configuration vs. Chip Mode .......................... 28

5. Data Processing....................................................................... 29

5.1. Overview.......................................................................... 29

5.1.1. Block Diagram......................................................... 29

5.1.2. Data Operation Modes ............................................ 29

5.2. Control Block Description ................................................ 30

5.2.1. SPI Interface ........................................................... 30

5.2.2. FIFO ........................................................................ 32

5.2.3. Sync Word Recognition........................................... 34

5.2.4. Packet Handler........................................................ 35

5.2.5. Control..................................................................... 35

5.3. Continuous Mode ............................................................ 36

5.3.1. General Description .................................................36

5.3.2. Rx Processing ..........................................................37

5.3.3. Interrupt Signals Mapping ........................................37

5.3.4. uC Connections........................................................38

5.3.5. Continuous Mode Example ......................................38

5.4. Buffered Mode ..................................................................39

5.4.1. General Description .................................................39

5.4.2. Rx Processing ..........................................................39

5.4.3. Interrupt Signals Mapping ........................................40

5.4.4. uC Connections........................................................41

5.4.5. Buffered Mode Example...........................................41

5.5. Packet Mode.....................................................................42

5.5.1. General Description .................................................42

5.5.2. Packet Format..........................................................42

5.5.3. Rx Processing ..........................................................44

5.5.4. Packet Filtering ........................................................44

5.5.5. DC-Free Data Mechanisms......................................46

5.5.6. Interrupt Signal Mapping ..........................................47

5.5.7. uC Connections........................................................47

5.5.8. Packet Mode Example .............................................48

5.5.9. Additional Information ..............................................48

6. Configuration and Status Registers ..........................................49

6.1. General Description..........................................................49

6.2. Main Configuration Register - MCParam..........................49

6.3. Interrupt Configuration Parameters - IRQParam ..............51

6.4. Receiver Configuration parameters - RXParam ...............53

6.5. Sync Word Parameters - SYNCParam.............................54

6.6. Oscillator Parameters - OSCParam .................................55

6.7. Packet Handling Parameters – PKTParam ......................56

7. Application Information .............................................................57

7.1. Crystal Resonator Specification .......................................57

7.2. Software for Frequency Calculation .................................57

7.2.1. GUI...........................................................................57

7.2.2. .dll for Automatic Production Bench .........................57

7.3. Switching Times and Procedures .....................................57

7.3.1. Optimized Receive Cycle .........................................58

7.3.2. Receiver Frequency Hop Optimized Cycle ..............59

7.4. Reset of the Chip..............................................................60

7.4.1. POR .........................................................................60

7.4.2. Manual Reset ...........................................................60

7.5. Reference Design.............................................................61

7.5.1. Application Schematic..............................................61

7.5.2. PCB Layout ..............................................................61

7.5.3. Bill Of Material..........................................................62

7.5.4. Ordering Information for Tools .................................63

8. Packaging Information ..............................................................63

8.1. Package Outline Drawing .................................................63

8.2. PCB Land Pattern.............................................................64

8.3. Tape & Reel Specification ................................................64

9. Revision History ........................................................................65

10. Contact Information.................................................................65

SX1213

ADVANCED COMMUNICATIONS & SENSING

Rev.2 – July 1

, 2009 Page 3 of 65 www.semtech.com

Index of Figures

Figure 1: SX1213 Simplified Block Diagram .................................. 5

Figure 2: SX1213 Pin Diagram ...................................................... 6

Figure 3: SX1213 Detailed Block Diagram .................................. 12

Figure 4: Power Supply Breakdown............................................. 13

Figure 5: Frequency Synthesizer Description .............................. 14

Figure 6: LO Generator ................................................................ 14

Figure 7: Loop Filter ..................................................................... 16

Figure 8: Receiver Architecture ................................................... 18

Figure 9: FSK Receiver Setting ................................................... 18

Figure 10: OOK Receiver Setting ................................................ 18

Figure 11: Active Channel Filter Description................................ 19

Figure 12: Butterworth Filter's Actual BW .................................... 21

Figure 13: Polyphase Filter's Actual BW...................................... 21

Figure 14: RSSI Dynamic Range................................................. 22

Figure 15: RSSI IRQ Timings ...................................................... 23

Figure 16: OOK Demodulator Description ................................... 24

Figure 17: Floor Threshold Optimization...................................... 25

Figure 18: BitSync Description..................................................... 26

Figure 19: SX1213’s Data Processing Conceptual View ............. 29

Figure 20: SPI Interface Overview and uC Connections ............. 30

Figure 21: Write Register Sequence ............................................ 31

Figure 22: Read Register Sequence............................................ 32

Figure 23: Read Bytes Sequence (ex: 2 bytes) ........................... 32

Figure 24: FIFO and Shift Register (SR)...................................... 33

Figure 25: FIFO Threshold IRQ Source Behavior........................ 34

Figure 26: Sync Word Recognition .............................................. 34

Figure 27: Continuous Mode Conceptual View.............................36

Figure 28: Rx Processing in Continuous Mode.............................37

Figure 29: uC Connections in Continuous Mode ..........................38

Figure 30: Buffered Mode Conceptual View .................................39

Figure 31: Rx Processing in Buffered Mode (FIFO size=16,

Fifo_fill_method=0).............................................................40

Figure 32: uC Connections in Buffered Mode...............................41

Figure 33: Packet Mode Conceptual View....................................42

Figure 34: Fixed Length Packet Format........................................43

Figure 35: Variable Length Packet Format ...................................44

Figure 36: CRC Implementation ...................................................46

Figure 37: Manchester Decoding..................................................46

Figure 38: Data Whitening Implementation...................................47

Figure 39: uC Connections in Packet Mode .................................47

Figure 40: Optimized Rx Cycle .....................................................58

Figure 41: Rx Hop Cycle...............................................................59

Figure 42: POR Timing Diagram...................................................60

Figure 43: Manual Reset Timing Diagram ....................................60

Figure 44: Reference Design Circuit Schematic ...........................61

Figure 45: Reference Design‘s Stackup .......................................62

Figure 46: Reference Design Layout (top view)............................62

Figure 47: Package Outline Drawing ............................................63

Figure 48: PCB Land Pattern........................................................64

Figure 49: Tape & Reel Dimensions .............................................64

SX1213

ADVANCED COMMUNICATIONS & SENSING

Rev.2 – July 1

, 2009 Page 4 of 65 www.semtech.com

Index of Tables

Table 1: Ordering Information ........................................................ 1

Table 2: SX1213 Pinouts ............................................................... 7

Table 3: Absolute Maximum Ratings ............................................. 8

Table 4: Operating Range.............................................................. 8

Table 5: Power Consumption Specification ................................... 8

Table 6: Frequency Synthesizer Specification............................... 9

Table 7: Receiver Specification.................................................... 10

Table 8: Digital Specification (1) .................................................. 11

Table 9: MCParam_Freq_band and MCParam_Subband Setting

.......................................................................................... 15

Table 10: Operating Modes ......................................................... 28

Table 11: Pin Configuration vs. Chip Mode ................................. 28

Table 12: Data Operation Mode Selection................................... 30

Table 13: Config vs. Data SPI Interface Selection....................... 31

Table 14: Status of FIFO when Switching Between Different

Modes of the Chip ............................................................. 34

Table 15: Interrupt Mapping in Continuous Rx Mode .................. 37

Table 16: Relevant Configuration Registers in Continuous Mode

(data processing related only)............................................38

Table 17: Interrupt Mapping in Buffered Rx and Stby Modes .......40

Table 18: Relevant Configuration Registers in Buffered Mode (data

processing related only) .....................................................41

Table 19: Interrupt Mapping in Rx and Stby in Packet Mode........47

Table 20: Relevant Configuration Registers in Packet Mode (data

processing related only) .....................................................48

Table 21: Registers List ................................................................49

Table 22: MCParam Register Description ....................................49

Table 23: IRQParam Register Description....................................51

Table 24: RXParam Register Description .....................................53

Table 25: SYNCParam Register Description ................................54

Table 26: OSCParam Register Description ..................................55

Table 27: PKTParam Register Description ...................................56

Table 28: Crystal Resonator Specification....................................57

Table 29: Reference Design BOM ................................................62

Table 30: Tools Ordering Information ...........................................63

Acronyms

BOM Bill Of Materials

BR Bit Rate

BW Bandwidth

CCITT

Comité Consultatif International

Téléphonique et Télégraphique - ITU

CP Charge Pump

CRC Cyclic Redundancy Check

DAC Digital to Analog Converter

DDS Direct Digital Synthesis

DLL Dynamically Linked Library

ERP

Equivalent Radiated Power

ETSI

European Telecommunications Standards

Institute

FCC Federal Communications Commission

Fdev Frequency Deviation

FIFO First In First Out

FS Frequency Synthesizer

FSK Frequency Shift Keying

GUI Graphical User Interface

IC Integrated Circuit

ID IDentificator

IF Intermediate Frequency

IRQ Interrupt ReQuest

ITU International Telecommunication Union

LFSR Linear Feedback Shift Register

LNA Low Noise Amplifier

LO Local Oscillator

LSB Least Significant Bit

MSB Most Significant Bit

NRZ Non Return to Zero

NZIF Near Zero Intermediate Frequency

OOK On Off Keying

PA Power Amplifier

PCB Printed Circuit Board

PFD Phase Frequency Detector

PLL Phase-Locked Loop

POR Power On Reset

RBW Resolution BandWidth

RF Radio Frequency

RSSI Received Signal Strength Indicator

Rx Receiver

SAW Surface Acoustic Wave

SPI Serial Peripheral Interface

SR Shift Register

Stby Standby

Tx Transmitter

uC Microcontroller

VCO Voltage Controlled Oscillator

XO Crystal Oscillator

XOR eXclusive OR

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