372 ■ Chapter Five Thread-Level Parallelism
misses. With a larger L3, these two sources shrink to be minor contributors.
Unfortunately, the compulsory, false sharing, and true sharing misses are unaf-
fected by a larger L3. Thus, at 4 MB and 8 MB, the true sharing misses gener-
ate the dominant fraction of the misses; the lack of change in true sharing
misses leads to the limited reductions in the overall miss rate when increasing
the L3 cache size beyond 2 MB.
Increasing the cache size eliminates most of the uniprocessor misses while
leaving the multiprocessor misses untouched. How does increasing the processor
count affect different types of misses? Figure 5.14 shows these data assuming a
base configuration with a 2 MB, two-way set associative L3 cache. As we might
expect, the increase in the true sharing miss rate, which is not compensated for by
any decrease in the uniprocessor misses, leads to an overall increase in the mem-
ory access cycles per instruction.
The final question we examine is whether increasing the block size—which
should decrease the instruction and cold miss rate and, within limits, also reduce
the capacity/conflict miss rate and possibly the true sharing miss rate—is helpful
for this workload. Figure 5.15 shows the number of misses per 1000 instructions
as the block size is increased from 32 to 256 bytes. Increasing the block size from
32 to 256 bytes affects four of the miss rate components:
■ The true sharing miss rate decreases by more than a factor of 2, indicating
some locality in the true sharing patterns.
■ The compulsory miss rate significantly decreases, as we would expect.
Figure 5.14 The contribution to memory access cycles increases as processor count
increases primarily due to increased true sharing. The compulsory misses slightly
increase since each processor must now handle more compulsory misses.
3
2.5
2
1.5
1
0.5
0
Memory cycles per instruction
1 2 4 6 8
Processor count
Compulsory
Capacity/conflict
False sharing
Instruction
True sharing
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