PCI Express Architecture PHY Test Specification | 5
Revision 5.0, Version 1.0
Mar 28, 2022
2.9.1 Starting Configuration .............................................................................................................. 34
2.9.2 Overview of Test Steps ........................................................................................................... 34
2.9.3 System Board Transmitter Electrical Compliance Test for 2.5 GT/s and 5.0 GT/s ................. 35
2.9.4 System Board Transmitter Electrical Compliance Test for 8.0 GT/s ....................................... 36
2.9.5 System Board Transmitter Electrical Compliance Test for 16.0 GT/s ..................................... 37
2.9.6 System Board Transmitter Electrical Compliance Test for 32.0 GT/s ..................................... 38
2.10 System Board Transmitter Jitter Test at 32.0 GT/s ...................................................................................... 39
2.10.1 Starting Configuration .............................................................................................................. 39
2.10.2 Overview of Test Steps ........................................................................................................... 39
2.11 System Board Transmitter Preset Test ........................................................................................................ 41
2.11.1 Starting Configuration .............................................................................................................. 41
2.11.2 System Board Transmitter Preset Test for 8.0 GT/s ............................................................... 41
2.11.3 System Board Transmitter Preset Test for 16.0 GT/s ............................................................. 42
2.11.4 System Board Transmitter Preset Test for 32.0 GT/s ............................................................. 42
2.12 System Board Transmitter Link Equalization Response Test ....................................................................... 44
2.12.1 Starting Configuration .............................................................................................................. 44
2.12.2 System Board Transmitter Link Equalization Response Test for 8.0 GT/s ............................. 44
2.12.3 System Board Transmitter Link Equalization Response Test for 16.0 GT/s ........................... 46
2.12.4 System Board Transmitter Link Equalization Response Test for 32.0 GT/s ........................... 48
2.13 System Lane Margining at 16.0 GT/s ........................................................................................................... 50
2.14 System Lane Margining at 32.0 GT/s ........................................................................................................... 51
2.15 Add-in Card Receiver Link Equalization Test ............................................................................................... 52
2.15.1 Starting Configuration, Overview of Calibration Steps at 8.0 GT/s ......................................... 52
2.15.2 Overview of Calibration Steps at 16.0 GT/s ............................................................................ 55
2.15.3 Overview of Calibration Steps at 32.0 GT/s ............................................................................ 61
2.15.4 Add-in Card Receiver Link Equalization Test for 8.0 GT/s ...................................................... 67
2.15.5 Add-in Card Receiver Link Equalization Test for 16.0 GT/s .................................................... 68
2.15.6 Add-in Card Receiver Link Equalization Test for 32.0 GT/s .................................................... 69
2.16 System Receiver Link Equalization Test ....................................................................................................... 70
2.16.1 Starting Configuration, Overview of Calibration Steps at 8.0 GT/s ......................................... 70
2.16.2 Overview of Calibration Steps at 16.0 GT/s ............................................................................ 70
2.16.3 Overview of Calibration Steps at 32.0 GT/s ............................................................................ 70
2.16.4 System Board Receiver Link Equalization Test for 8.0 GT/s .................................................. 70
2.16.5 System Board Receiver Link Equalization Test for 16.0 GT/s ................................................ 71
2.16.6 System Board Receiver Link Equalization Test for 32.0 GT/s ................................................ 72
2.17 System Board Reference Clock (100 MHz) Jitter Test ................................................................................. 73
2.18 Add-in Card PLL Bandwidth Test ................................................................................................................. 74
2.18.1 Starting Configuration .............................................................................................................. 74
2.18.2 Overview of Test Steps ........................................................................................................... 74
Appendix A. PCIe 4.0 Electrical Test Fixture Characterization ............................................................. 77
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