PHY Interface for the PCI Express
TM
Architecture
©2007 Intel Corporation—All rights reserved. Page 3 of 38
Table of Contents
1 Preface...................................................................................................................................... 5
1.1 Scope of this Revision ...................................................................................................... 5
1.2 Revision History ............................................................................................................... 5
2 Introduction.............................................................................................................................. 6
2.1 PCI Express PHY Layer ................................................................................................... 7
3 PHY/MAC Interface ................................................................................................................ 7
4 PCI Express PHY Functionality............................................................................................... 9
4.1 Transmitter Block Diagram ............................................................................................ 10
4.2 Receiver Block Diagram................................................................................................. 11
4.3 Clocking.......................................................................................................................... 11
5 PIPE Interface Signal Descriptions........................................................................................ 12
5.1 PHY/MAC Interface Signals .......................................................................................... 12
5.2 External Signals .............................................................................................................. 15
6 PIPE Operational Behavior.................................................................................................... 17
6.1 Clocking.......................................................................................................................... 17
6.2 Reset................................................................................................................................ 17
6.3 Power Management ........................................................................................................ 17
6.4 Receiver Detection.......................................................................................................... 19
6.5 Transmitting a beacon..................................................................................................... 22
6.6 Detecting a beacon.......................................................................................................... 22
6.7 Clock Tolerance Compensation...................................................................................... 23
6.8 Error Detection................................................................................................................ 24
6.8.1 8B/10B Decode Errors............................................................................................. 24
6.8.2 Disparity Errors ....................................................................................................... 25
6.8.3 Elastic Buffer Errors................................................................................................ 25
6.9 Loopback ........................................................................................................................26
6.10 Polarity Inversion........................................................................................................ 28
6.11 Setting negative disparity............................................................................................ 28
6.12 Implementation specific timing................................................................................... 29
6.13 Control Signal Decode table........................................................................................ 31
6.14 Recommended synchronous signal timings ................................................................ 32
7 Sample Operational Sequences.............................................................................................. 32
7.1 Active PM L0 to L0s and back to L0.............................................................................. 32
7.2 Active PM to L1 and back to L0..................................................................................... 33
7.3 Receivers and Electrical Idle .......................................................................................... 34
8 Multi-lane PIPE...................................................................................................................... 37
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xyele_liyi2014-05-21讲的是PHY层的相关知识，非PHY层测试的规范！！
xinjian8232014-02-20资源不错，很有用，谢谢
木已成舟ytx2015-04-18这是Inter出的物理层相关接口规范
