STM8S系列说有的头文件

/* STM8S128K.h */ /* Copyright (c) 2003-2014 STMicroelectronics */ #ifndef __STM8S128K__ #define __STM8S128K__ /* STM8S128K */ /* Check MCU name */ #ifdef MCU_NAME #define STM8S128K 1 #if (MCU_NAME != STM8S128K) #error "wrong include file STM8S128K.h for chosen MCU!" #endif #endif #ifdef __CSMC__ #define DEF_8BIT_REG_AT(NAME,ADDRESS) volatile unsigned char NAME @ADDRESS #define DEF_16BIT_REG_AT(NAME,ADDRESS) volatile unsigned int NAME @ADDRESS #endif #ifdef __RAISONANCE__ #define DEF_8BIT_REG_AT(NAME,ADDRESS) at ADDRESS hreg NAME #define DEF_16BIT_REG_AT(NAME,ADDRESS) at ADDRESS hreg16 NAME #endif /* Port A */ /*****************************************************************/ /* Port A data output latch register */ DEF_8BIT_REG_AT(PA_ODR,0x5000); /* Port A input pin value register */ DEF_8BIT_REG_AT(PA_IDR,0x5001); /* Port A data direction register */ DEF_8BIT_REG_AT(PA_DDR,0x5002); /* Port A control register 1 */ DEF_8BIT_REG_AT(PA_CR1,0x5003); /* Port A control register 2 */ DEF_8BIT_REG_AT(PA_CR2,0x5004); /* Port B */ /*****************************************************************/ /* Port B data output latch register */ DEF_8BIT_REG_AT(PB_ODR,0x5005); /* Port B input pin value register */ DEF_8BIT_REG_AT(PB_IDR,0x5006); /* Port B data direction register */ DEF_8BIT_REG_AT(PB_DDR,0x5007); /* Port B control register 1 */ DEF_8BIT_REG_AT(PB_CR1,0x5008); /* Port B control register 2 */ DEF_8BIT_REG_AT(PB_CR2,0x5009); /* Port C */ /*****************************************************************/ /* Port C data output latch register */ DEF_8BIT_REG_AT(PC_ODR,0x500a); /* Port C input pin value register */ DEF_8BIT_REG_AT(PC_IDR,0x500b); /* Port C data direction register */ DEF_8BIT_REG_AT(PC_DDR,0x500c); /* Port C control register 1 */ DEF_8BIT_REG_AT(PC_CR1,0x500d); /* Port C control register 2 */ DEF_8BIT_REG_AT(PC_CR2,0x500e); /* Port D */ /*****************************************************************/ /* Port D data output latch register */ DEF_8BIT_REG_AT(PD_ODR,0x500f); /* Port D input pin value register */ DEF_8BIT_REG_AT(PD_IDR,0x5010); /* Port D data direction register */ DEF_8BIT_REG_AT(PD_DDR,0x5011); /* Port D control register 1 */ DEF_8BIT_REG_AT(PD_CR1,0x5012); /* Port D control register 2 */ DEF_8BIT_REG_AT(PD_CR2,0x5013); /* Port E */ /*****************************************************************/ /* Port E data output latch register */ DEF_8BIT_REG_AT(PE_ODR,0x5014); /* Port E input pin value register */ DEF_8BIT_REG_AT(PE_IDR,0x5015); /* Port E data direction register */ DEF_8BIT_REG_AT(PE_DDR,0x5016); /* Port E control register 1 */ DEF_8BIT_REG_AT(PE_CR1,0x5017); /* Port E control register 2 */ DEF_8BIT_REG_AT(PE_CR2,0x5018); /* Port F */ /*****************************************************************/ /* Port F data output latch register */ DEF_8BIT_REG_AT(PF_ODR,0x5019); /* Port F input pin value register */ DEF_8BIT_REG_AT(PF_IDR,0x501a); /* Port F data direction register */ DEF_8BIT_REG_AT(PF_DDR,0x501b); /* Port F control register 1 */ DEF_8BIT_REG_AT(PF_CR1,0x501c); /* Port F control register 2 */ DEF_8BIT_REG_AT(PF_CR2,0x501d); /* Port G */ /*****************************************************************/ /* Port G data output latch register */ DEF_8BIT_REG_AT(PG_ODR,0x501e); /* Port G input pin value register */ DEF_8BIT_REG_AT(PG_IDR,0x501f); /* Port G data direction register */ DEF_8BIT_REG_AT(PG_DDR,0x5020); /* Port G control register 1 */ DEF_8BIT_REG_AT(PG_CR1,0x5021); /* Port G control register 2 */ DEF_8BIT_REG_AT(PG_CR2,0x5022); /* Port H */ /*****************************************************************/ /* Port H data output latch register */ DEF_8BIT_REG_AT(PH_ODR,0x5023); /* Port H input pin value register */ DEF_8BIT_REG_AT(PH_IDR,0x5024); /* Port H data direction register */ DEF_8BIT_REG_AT(PH_DDR,0x5025); /* Port H control register 1 */ DEF_8BIT_REG_AT(PH_CR1,0x5026); /* Port H control register 2 */ DEF_8BIT_REG_AT(PH_CR2,0x5027); /* Port I */ /*****************************************************************/ /* Port I data output latch register */ DEF_8BIT_REG_AT(PI_ODR,0x5028); /* Port I input pin value register */ DEF_8BIT_REG_AT(PI_IDR,0x5029); /* Port I data direction register */ DEF_8BIT_REG_AT(PI_DDR,0x502a); /* Port I control register 1 */ DEF_8BIT_REG_AT(PI_CR1,0x502b); /* Port I control register 2 */ DEF_8BIT_REG_AT(PI_CR2,0x502c); /* Flash */ /*****************************************************************/ /* Flash control register 1 */ DEF_8BIT_REG_AT(FLASH_CR1,0x505a); /* Flash control register 2 */ DEF_8BIT_REG_AT(FLASH_CR2,0x505b); /* Flash complementary control register 2 */ DEF_8BIT_REG_AT(FLASH_NCR2,0x505c); /* Flash protection register */ DEF_8BIT_REG_AT(FLASH_FPR,0x505d); /* Flash complementary protection register */ DEF_8BIT_REG_AT(FLASH_NFPR,0x505e); /* Flash in-application programming status register */ DEF_8BIT_REG_AT(FLASH_IAPSR,0x505f); /* Flash Program memory unprotection register */ DEF_8BIT_REG_AT(FLASH_PUKR,0x5062); /* Data EEPROM unprotection register */ DEF_8BIT_REG_AT(FLASH_DUKR,0x5064); /* External Interrupt Control Register (ITC) */ /*****************************************************************/ /* External interrupt control register 1 */ DEF_8BIT_REG_AT(EXTI_CR1,0x50a0); /* External interrupt control register 2 */ DEF_8BIT_REG_AT(EXTI_CR2,0x50a1); /* Reset (RST) */ /*****************************************************************/ /* Reset status register 1 */ DEF_8BIT_REG_AT(RST_SR,0x50b3); /* Clock Control (CLK) */ /*****************************************************************/ /* Internal clock control register */ DEF_8BIT_REG_AT(CLK_ICKR,0x50c0); /* External clock control register */ DEF_8BIT_REG_AT(CLK_ECKR,0x50c1); /* Clock master status register */ DEF_8BIT_REG_AT(CLK_CMSR,0x50c3); /* Clock master switch register */ DEF_8BIT_REG_AT(CLK_SWR,0x50c4); /* Clock switch control register */ DEF_8BIT_REG_AT(CLK_SWCR,0x50c5); /* Clock divider register */ DEF_8BIT_REG_AT(CLK_CKDIVR,0x50c6); /* Peripheral clock gating register 1 */ DEF_8BIT_REG_AT(CLK_PCKENR1,0x50c7); /* Clock security system register */ DEF_8BIT_REG_AT(CLK_CSSR,0x50c8); /* Configurable clock control register */ DEF_8BIT_REG_AT(CLK_CCOR,0x50c9); /* Peripheral clock gating register 2 */ DEF_8BIT_REG_AT(CLK_PCKENR2,0x50ca); /* CAN clock control register */ DEF_8BIT_REG_AT(CLK_CANCCR,0x50cb); /* HSI clock calibration trimming register */ DEF_8BIT_REG_AT(CLK_HSITRIMR,0x50cc); /* SWIM clock control register */ DEF_8BIT_REG_AT(CLK_SWIMCCR,0x50cd); /* Window Watchdog (WWDG) */ /*****************************************************************/ /* WWDG Control Register */ DEF_8BIT_REG_AT(WWDG_CR,0x50d1); /* WWDR Window Register */ DEF_8BIT_REG_AT(WWDG_WR,0x50d2); /* Independent Watchdog (IWDG) */ /*****************************************************************/ /* IWDG Key Register */ DEF_8BIT_REG_AT(IWDG_KR,0x50e0); /* IWDG Prescaler Register */ DEF_8BIT_REG_AT(IWDG_PR,0x50e1); /* IWDG Reload Register */ DEF_8BIT_REG_AT(IWDG_RLR,0x50e2); /* Auto Wake-Up (AWU) */ /*****************************************************************/ /* AWU Control/Status Register */ DEF_8BIT_REG_AT(AWU_CSR,0x50f0); /* AWU asynchronous prescaler buffer register */ DEF_8BIT_REG_AT(AWU_APR,0x50f1); /* AWU Timebase selection register */ DEF_8BIT_REG_AT(AWU_TBR,0x50f2); /* Beeper (BEEP) */ /*****************************************************************/ /* BEEP Control/Status Register */ DEF_8BIT_REG_AT(BEEP_CSR,0x50f3); /* Serial Peripheral Interface (SPI) */ /**************