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<title>Sample Waveforms for DOUBLRAM.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file DOUBLRAM.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design DOUBLRAM.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design DOUBLRAM.vhd has one read port and one write port. The read port has 256 words of 8 bits each and the write port has 256 words of 8 bits each. The output of the read port is registered by clock. </P>
<CENTER><img src=DOUBLRAM_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. Read enable port should be enabled for read in the simple dual port mode The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=DOUBLRAM_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the falling edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. </P>
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双口RAM读写，FPGA，VHDL语言
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2011-08-26
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双口RAM读写，FPGA，VHDL语言 （212个子文件） 
testRAMWR.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.atm 23KB testRAMWR.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm 20KB testRAMWR.root_partition.cmp.atm 11KB testRAMWR.root_partition.map.atm 11KB fifo3.vhd.bak 637B ADDRESS.vhd.bak 497B ADD8B.vhd.bak 483B Delay.vhd.bak 263B testRAMWR.bdf 8KB testRAMWR.cmp.bpm 662B testRAMWR.map.bpm 633B DOUBLRAM.bsf 5KB IIPORTRAM.bsf 5KB RAMWR.bsf 4KB FIFO.bsf 3KB ADDRESS.bsf 2KB ADD8B.bsf 2KB testRAMWR.(9).cnf.cdb 8KB testRAMWR.(7).cnf.cdb 6KB testRAMWR.cmp.cdb 5KB testRAMWR.(8).cnf.cdb 5KB testRAMWR.(17).cnf.cdb 5KB testRAMWR.rtlv_sg.cdb 4KB testRAMWR.(10).cnf.cdb 3KB testRAMWR.pre_map.cdb 2KB testRAMWR.(11).cnf.cdb 2KB testRAMWR.map.cdb 2KB testRAMWR.(13).cnf.cdb 2KB testRAMWR.(6).cnf.cdb 2KB testRAMWR.(23).cnf.cdb 2KB testRAMWR.(20).cnf.cdb 2KB testRAMWR.(25).cnf.cdb 2KB testRAMWR.(31).cnf.cdb 2KB testRAMWR.rtlv_sg_swap.cdb 2KB testRAMWR.(3).cnf.cdb 2KB testRAMWR.(22).cnf.cdb 2KB testRAMWR.(5).cnf.cdb 2KB testRAMWR.(19).cnf.cdb 2KB testRAMWR.(27).cnf.cdb 2KB testRAMWR.(33).cnf.cdb 2KB testRAMWR.(26).cnf.cdb 1KB testRAMWR.(32).cnf.cdb 1KB testRAMWR.sgdiff.cdb 1KB testRAMWR.(29).cnf.cdb 1KB testRAMWR.(18).cnf.cdb 1KB testRAMWR.(21).cnf.cdb 1KB testRAMWR.(4).cnf.cdb 1KB testRAMWR.(1).cnf.cdb 1KB testRAMWR.(0).cnf.cdb 1KB testRAMWR.(2).cnf.cdb 1KB testRAMWR.(30).cnf.cdb 998B testRAMWR.(15).cnf.cdb 987B testRAMWR.(28).cnf.cdb 940B testRAMWR.(24).cnf.cdb 940B testRAMWR.(16).cnf.cdb 934B testRAMWR.(12).cnf.cdb 890B testRAMWR.map_bb.cdb 772B testRAMWR.(14).cnf.cdb 636B testRAMWR.signalprobe.cdb 296B testRAMWR.eco.cdb 161B DOUBLRAM.cmp 1KB FIFO.cmp 1KB IIPORTRAM.cmp 1KB RAMWR.cmp 1KB testRAMWR.sim.cvwf 2KB testRAMWR.db_info 137B testRAMWR.cmp0.ddb 58KB testRAMWR.cmp2.ddb 42KB testRAMWR.asm_labs.ddb 3KB testRAMWR.tis_db_list.ddb 174B testRAMWR.root_partition.cmp.dfp 33B testRAMWR.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.dfp 33B testRAMWR.done 26B testRAMWR.map.ecobp 28B testRAMWR.cmp.ecobp 28B testRAMWR.eds_overflow 3B testRAMWR.sgdiff.hdb 12KB testRAMWR.pre_map.hdb 12KB testRAMWR.rtlv.hdb 12KB testRAMWR.map.hdb 10KB testRAMWR.cmp.hdb 10KB testRAMWR.map_bb.hdb 7KB testRAMWR.sim.hdb 4KB testRAMWR.(9).cnf.hdb 3KB testRAMWR.(7).cnf.hdb 2KB testRAMWR.(8).cnf.hdb 1KB testRAMWR.(17).cnf.hdb 1KB testRAMWR.(13).cnf.hdb 1006B testRAMWR.(20).cnf.hdb 782B testRAMWR.(23).cnf.hdb 781B testRAMWR.(6).cnf.hdb 780B testRAMWR.(26).cnf.hdb 726B testRAMWR.(10).cnf.hdb 726B testRAMWR.(32).cnf.hdb 723B testRAMWR.(21).cnf.hdb 720B testRAMWR.(18).cnf.hdb 719B testRAMWR.(25).cnf.hdb 713B testRAMWR.(27).cnf.hdb 712B testRAMWR.(4).cnf.hdb 711B testRAMWR.(33).cnf.hdb 710B共 212 条
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