4 Datasheet
5.6 DMA Operation (D31:F0) .................................................................................. 101
5.6.1 Channel Priority................................................................................. 102
5.6.2 Address Compatibility Mode ................................................................ 102
5.6.3 Summary of DMA Transfer Sizes..........................................................102
5.6.4 Autoinitialize ..................................................................................... 103
5.6.5 Software Commands ..........................................................................103
5.7 LPC DMA ........................................................................................................ 104
5.7.1 Asserting DMA Requests ..................................................................... 104
5.7.2 Abandoning DMA Requests..................................................................104
5.7.3 General Flow of DMA Transfers ............................................................ 105
5.7.4 Terminal Count.................................................................................. 105
5.7.5 Verify Mode ......................................................................................105
5.7.6 DMA Request Deassertion ................................................................... 106
5.7.7 SYNC Field / LDRQ# Rules ..................................................................106
5.8 8254 Timers (D31:F0) ...................................................................................... 107
5.8.1 Timer Programming ........................................................................... 107
5.8.2 Reading from the Interval Timer .......................................................... 108
5.9 8259 Interrupt Controllers (PIC) (D31:F0)........................................................... 110
5.9.1 Interrupt Handling .............................................................................111
5.9.2 Initialization Command Words (ICWx) ..................................................112
5.9.3 Operation Command Words (OCW) ......................................................113
5.9.4 Modes of Operation............................................................................ 113
5.9.5 Masking Interrupts.............................................................................115
5.9.6 Steering PCI Interrupts ......................................................................116
5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0)............................... 117
5.10.1 Interrupt Handling .............................................................................117
5.10.2 Interrupt Mapping.............................................................................. 117
5.10.3 PCI / PCI Express* Message-Based Interrupts .......................................118
5.10.4 External Interrupt Controller Support ...................................................118
5.11 Serial Interrupt (D31:F0).................................................................................. 119
5.11.1 Start Frame ......................................................................................119
5.11.2 Data Frames .....................................................................................119
5.11.3 Stop Frame....................................................................................... 120
5.11.4 Specific Interrupts Not Supported using SERIRQ .................................... 120
5.11.5 Data Frame Format............................................................................ 121
5.12 Real Time Clock (D31:F0) ................................................................................. 122
5.12.1 Update Cycles ...................................................................................122
5.12.2 Interrupts.........................................................................................123
5.12.3 Lockable RAM Ranges......................................................................... 123
5.12.4 Century Rollover................................................................................123
5.12.5 Clearing Battery-Backed RTC RAM........................................................ 123
5.13 Processor Interface (D31:F0) ............................................................................ 125
5.13.1 Processor Interface Signals and VLW Messages...................................... 125
5.13.2 Dual-Processor Issues ........................................................................127
5.13.3 Virtual Legacy Wire (VLW) Messages .................................................... 127
5.14 Power Management..........................................................................................127
5.14.1 Features........................................................................................... 127
5.14.2 PCH and System Power States............................................................. 128
5.14.3 System Power Planes .........................................................................129
5.14.4 SMI#/SCI Generation......................................................................... 130
5.14.5 C-States........................................................................................... 132
5.14.6 Sleep States .....................................................................................133
5.14.7 Event Input Signals and Their Usage ....................................................137
5.14.8 ALT Access Mode ...............................................................................140
5.14.9 System Power Supplies, Planes, and Signals..........................................143
5.14.10 Legacy Power Management Theory of Operation .................................... 145
5.14.11 Reset Behavior ..................................................................................145
5.15 System Management (D31:F0) .......................................................................... 147
5.15.1 Theory of Operation ........................................................................... 147
5.15.2 TCO Modes .......................................................................................148
5.16 General Purpose I/O (D31:F0) ...........................................................................150
5.16.1 Power Wells ...................................................................................... 150
5.16.2 SMI# SCI and NMI Routing ................................................................. 150
5.16.3 Triggering......................................................................................... 150
5.16.4 GPIO Registers Lockdown ...................................................................151
5.16.5 Serial POST Codes over GPIO ..............................................................151
5.16.6 GPIO Serial Expander (GSX) ............................................................... 154