MT7688_Datasheet_v1_4资源-CSDN文库

MT7688

需积分: 32 96 浏览量 2017-03-16 22:08:13 上传评论收藏 6.6MB PDF 举报

资源详情

资源评论

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

MediaTek cannot grant you permission for any material that is owned by third parties. You may only use or

reproduce this document if you have agreed to and been granted explicit permission within the “License

Agreement” that is available on MediaTek’s website (“Permitted User”). If you are not a Permitted User,

please cease any access or use of this document immediately. Any unauthorized use, reproduction or

disclosure of this document in whole or in part is strictly prohibited. For more information, please consult your

legal advisor. Specifications contained herein are subject to change without notice.

MediaTek MT7688 Datasheet

Version: 1.4

Release date: 15th April 2016

MediaTek MT7688 Datasheet

Page 3 of 317

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

Table of Contents

DOCUMENT REVISION HISTORY 2

1. OVERVIEW 7

1.1 FEATURES 7

2. MAIN FEATURES 9

3. PINS 10

3.1 MT7688AN DR-QFN (12 MM X 12 MM) 156-PIN PACKAGE DIAGRAM 10

3.1.1 UP-LEFT SIDE 10

3.1.2 DOWN-LEFT SIDE 11

3.1.3 DOWN-RIGHT SIDE 12

3.1.4 UP-RIGHT SIDE 13

3.1.5 PIN DESCRIPTION 14

3.2 MT7688KN DR-QFN (10 MM X 10 MM) 120-PIN PACKAGE DIAGRAM 20

3.2.1 LEFT SIDE VIE 20

3.2.2 RIGHT SIDE VIEW 21

3.2.3 PIN DESCRIPTION 22

3.3 PIN SHARING SCHEMES 25

3.3.1 GPIO PIN SHARE SCHEME 25

3.3.2 UART1 PIN SHARE SCHEME 26

3.3.3 MT7688AN EPHY LED PIN SHARE SCHEME 26

3.3.4 MT7688AN WLAN LED PIN SHARE SCHEME 27

3.3.5 MT7688KN EPHY LED PIN SHARE SCHEME 27

3.3.6 MT7688KN WLAN LED PIN SHARE SCHEME 27

3.3.7 PERST_N PIN SHARE SCHEME 27

3.3.8 WDT_RST_N PIN SHARE SCHEME 27

3.3.9 REF_CLKO PIN SHARE SCHEME 28

3.3.10 UART0 PIN SHARE SCHEME 28

3.3.11 GPIO0 PIN SHARE SCHEME 28

3.3.12 SPI PIN SHARE SCHEME 28

3.3.13 SPI_CS1 PIN SHARE SCHEME 28

3.3.14 I2C PIN SHARE SCHEME 28

3.3.15 I2S PIN SHARE SCHEME 28

3.3.16 SD PIN SHARE SCHEME 29

3.3.17 EMMC PIN SHARE SCHEME 29

3.3.18 UART2 PIN SHARE SCHEME 29

3.3.19 PWM_CH0 PIN SHARE SCHEME 29

3.3.20 PWM_CH1 PIN SHARE SCHEME 29

3.3.21 SPIS PIN SHARE SCHEME 30

3.3.22 PIN SHARE FUNCTION DESCRIPTION 30

3.4 BOOTSTRAPPING PINS DESCRIPTION 30

4. MAXIMUM RATINGS AND OPERATING CONDITIONS 32

4.1 ABSOLUTE MAXIMUM RATINGS 32

4.2 MAXIMUM TEMPERATURES 32

4.3 OPERATING CONDITIONS 32

4.4 THERMAL CHARACTERISTICS 32

4.5 STORAGE CONDITIONS 32

4.6 EXTERNAL XTAL SPECFICATION 33

4.7 DC ELECTRICAL CHARACTERISTICS 33

4.8 AC ELECTRICAL CHARACTERISTICS 34

4.8.1 DDR2 SDRAM INTERFACE 35

4.8.2 SPI INTERFACE 37

4.8.3 I

S INTERFACE 38

4.8.4 PCM INTERFACE 39

MediaTek MT7688 Datasheet

Page 5 of 317

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

5.14.4 PCM CONFIGURATION 163

5.14.5 REGISTER 164

5.15 GENERIC DMA CONTROLLER 180

5.15.1 FEATURES 180

5.15.2 BLOCK DIAGRAM 180

5.15.3 PERIPHERAL CHANNEL CONNECTION 180

5.15.4 REGISTERS 181

5.16 AES CONTROLLER 225

5.16.1 REGISTERS 225

5.17 PWM (PULSE WIDTH MODULATION) 233

5.17.1 REGISTERS 233

5.18 FRAME ENGINE 249

5.18.1 REGISTERS 249

5.19 SWITCH CONTROLLER 267

5.19.1 REGISTERS 267

6. ABBREVIATIONS 314

Table of Figures

IGURE 1-1 IOT DEVICE MODE FUCTIONAL BLOCK DIAGRAM .............................................................................................. 8

FIGURE 1-2 IOT GATEWAY MODE FUNCTIONAL BLOCK DIAGRAM ........................................................................................ 8

FIGURE 3-1 MT7688AN DR-QFN PIN DIAGRAM (UP-LEFT VIEW) .................................................................................... 10

FIGURE 3-2 MT7688AN DR-QFN PIN DIAGRAM (DOWN-LEFT VIEW) ............................................................................... 11

FIGURE 3-3 MT7688AN DR-QFN PIN DIAGRAM (DOWN-RIGHT VIEW) ............................................................................. 12

FIGURE 3-4 MT7688AN DR-QFN PIN DIAGRAM (UP-RIGHT VIEW) .................................................................................. 13

FIGURE 3-5 MT7688KN DR-QFN PIN DIAGRAM (LEFT VIEW) ......................................................................................... 20

FIGURE 3-6 MT7688KN DR-QFN PIN DIAGRAM (RIGHT SIDE VIEW) ................................................................................. 21

FIGURE 4-1 DDR2 SDRAM COMMAND ....................................................................................................................... 35

FIGURE 4-2 DDR2 SDRAM WRITE DATA ...................................................................................................................... 35

FIGURE 4-3 DDR2 SDRAM READ DATA ....................................................................................................................... 35

FIGURE 4-4 SPI INTERFACE ......................................................................................................................................... 37

FIGURE-4-5 I2S INTERFACE ......................................................................................................................................... 38

FIGURE 4-6 PCM INTERFACE ....................................................................................................................................... 39

FIGURE 4-7 POWER ON SEQUENCE .............................................................................................................................. 40

FIGURE 4-8 TOP VIEW................................................................................................................................................ 40

FIGURE 4-9 SIDE VIEW ............................................................................................................................................... 41

FIGURE 4-10 “B” EXPANDED ....................................................................................................................................... 41

FIGURE 4-11 BOTTON VIEW ........................................................................................................................................ 42

FIGURE 4-12 TOP VIEW.............................................................................................................................................. 43

FIGURE 4-13 SIDE VIEW ............................................................................................................................................. 44

FIGURE 4-14 “B” EXPANDED ....................................................................................................................................... 44

FIGURE 4-15 BOTTOM VIEW ....................................................................................................................................... 45

FIGURE 4-16 MT7688AN TOP MARKING ...................................................................................................................... 47

FIGURE 4-17 MT7688KN TOP MARKING ...................................................................................................................... 47

FIGURE 4-18 REFLOW PROFILE FOR MT7688 ................................................................................................................ 47

FIGURE 5-1 SYSTEM CONTROL BLOCK DIAGRAM ............................................................................................................. 49

FIGURE 5-2 TIMER BLOCK DIAGRAM ............................................................................................................................. 66

FIGURE 5-3 QOS ARBITRATION BLOCK DIAGRAM ............................................................................................................ 95

FIGURE 5-4 PROGRAMMABLE I/O BLOCK DIAGRAM ...................................................................................................... 107

FIGURE 5-5 I

S TRANSMITTER BLOCK DIAGRAM ............................................................................................................ 131

FIGURE 5-6 I2S TRANSMIT/RECEIVE ........................................................................................................................... 131

FIGURE 5-7 SPI CONTROLLER BLOCK DIAGRAM ............................................................................................................ 138

FIGURE 5-8 PCM CONTROLLER BLOCK DIAGRAM .......................................................................................................... 162