MediaTek MT7688 Datasheet
© 2016 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
5.14.4 PCM CONFIGURATION 163
5.14.5 REGISTER 164
5.15 GENERIC DMA CONTROLLER 180
5.15.1 FEATURES 180
5.15.2 BLOCK DIAGRAM 180
5.15.3 PERIPHERAL CHANNEL CONNECTION 180
5.15.4 REGISTERS 181
5.16 AES CONTROLLER 225
5.16.1 REGISTERS 225
5.17 PWM (PULSE WIDTH MODULATION) 233
5.17.1 REGISTERS 233
5.18 FRAME ENGINE 249
5.18.1 REGISTERS 249
5.19 SWITCH CONTROLLER 267
5.19.1 REGISTERS 267
6. ABBREVIATIONS 314
Table of Figures
F
IGURE 1-1 IOT DEVICE MODE FUCTIONAL BLOCK DIAGRAM .............................................................................................. 8
FIGURE 1-2 IOT GATEWAY MODE FUNCTIONAL BLOCK DIAGRAM ........................................................................................ 8
FIGURE 3-1 MT7688AN DR-QFN PIN DIAGRAM (UP-LEFT VIEW) .................................................................................... 10
FIGURE 3-2 MT7688AN DR-QFN PIN DIAGRAM (DOWN-LEFT VIEW) ............................................................................... 11
FIGURE 3-3 MT7688AN DR-QFN PIN DIAGRAM (DOWN-RIGHT VIEW) ............................................................................. 12
FIGURE 3-4 MT7688AN DR-QFN PIN DIAGRAM (UP-RIGHT VIEW) .................................................................................. 13
FIGURE 3-5 MT7688KN DR-QFN PIN DIAGRAM (LEFT VIEW) ......................................................................................... 20
FIGURE 3-6 MT7688KN DR-QFN PIN DIAGRAM (RIGHT SIDE VIEW) ................................................................................. 21
FIGURE 4-1 DDR2 SDRAM COMMAND ....................................................................................................................... 35
FIGURE 4-2 DDR2 SDRAM WRITE DATA ...................................................................................................................... 35
FIGURE 4-3 DDR2 SDRAM READ DATA ....................................................................................................................... 35
FIGURE 4-4 SPI INTERFACE ......................................................................................................................................... 37
FIGURE-4-5 I2S INTERFACE ......................................................................................................................................... 38
FIGURE 4-6 PCM INTERFACE ....................................................................................................................................... 39
FIGURE 4-7 POWER ON SEQUENCE .............................................................................................................................. 40
FIGURE 4-8 TOP VIEW................................................................................................................................................ 40
FIGURE 4-9 SIDE VIEW ............................................................................................................................................... 41
FIGURE 4-10 “B” EXPANDED ....................................................................................................................................... 41
FIGURE 4-11 BOTTON VIEW ........................................................................................................................................ 42
FIGURE 4-12 TOP VIEW.............................................................................................................................................. 43
FIGURE 4-13 SIDE VIEW ............................................................................................................................................. 44
FIGURE 4-14 “B” EXPANDED ....................................................................................................................................... 44
FIGURE 4-15 BOTTOM VIEW ....................................................................................................................................... 45
FIGURE 4-16 MT7688AN TOP MARKING ...................................................................................................................... 47
FIGURE 4-17 MT7688KN TOP MARKING ...................................................................................................................... 47
FIGURE 4-18 REFLOW PROFILE FOR MT7688 ................................................................................................................ 47
FIGURE 5-1 SYSTEM CONTROL BLOCK DIAGRAM ............................................................................................................. 49
FIGURE 5-2 TIMER BLOCK DIAGRAM ............................................................................................................................. 66
FIGURE 5-3 QOS ARBITRATION BLOCK DIAGRAM ............................................................................................................ 95
FIGURE 5-4 PROGRAMMABLE I/O BLOCK DIAGRAM ...................................................................................................... 107
FIGURE 5-5 I
2
S TRANSMITTER BLOCK DIAGRAM ............................................................................................................ 131
FIGURE 5-6 I2S TRANSMIT/RECEIVE ........................................................................................................................... 131
FIGURE 5-7 SPI CONTROLLER BLOCK DIAGRAM ............................................................................................................ 138
FIGURE 5-8 PCM CONTROLLER BLOCK DIAGRAM .......................................................................................................... 162
FIGURE 5-9 GENERIC DMA CONTROLLER BLOCK DIAGRAM ............................................................................................. 180
