2021.1:
* Version 12.0 (Rev. 6)
* General: Versal Pre-Production support
* Revision change in one or more subcores
2020.3:
* Version 12.0 (Rev. 5)
* General: H10 support enabled
2020.2.2:
* Version 12.0 (Rev. 4)
* No changes
2020.2.1:
* Version 12.0 (Rev. 4)
* General: Versal Pre-Production support
2020.2:
* Version 12.0 (Rev. 3)
* General: Aurora block automation updated for versal
* General: RPLL support added for versal
* Revision change in one or more subcores
2020.1.1:
* Version 12.0 (Rev. 2)
* No changes
2020.1:
* Version 12.0 (Rev. 2)
* General: GT Ref clock connections updated for greater than 16.375Gbps line rate and more than 4 lanes for versal devices
* General: GT TX and RX interface definitions modified for versal devices
* General: Changed user clk port definition to clock_rtl for versal devices
* General: Updated GTH based logic for crc valid genetaion.
* Revision change in one or more subcores
2019.2.2:
* Version 12.0 (Rev. 1)
* No changes
2019.2.1:
* Version 12.0 (Rev. 1)
* No changes
2019.2:
* Version 12.0 (Rev. 1)
* General: Updated loopback port connections in example design for Generate Aurora without GT option for TX/RX Simplex cases
* Revision change in one or more subcores
2019.1.3:
* Version 12.0
* No changes
2019.1.2:
* Version 12.0
* No changes
2019.1.1:
* Version 12.0
* No changes
2019.1:
* Version 12.0
* General: Added support for VERSAL devices
* General: Added support for AKINTEX7 devices
* Revision change in one or more subcores
2018.3.1:
* Version 11.2 (Rev. 6)
* No changes
2018.3:
* Version 11.2 (Rev. 6)
* Bug Fix: Improved performance in streaming mode for GTY devices when neither of UFC/NFC/USER-K is enabled.
* Bug Fix: Corrected bits assignment of txdiffctrl signal from 4 bits to 5 bits.
* Bug Fix: Updated the display range of RX_PPM_OFFSET to match UltraScale/UltraScale+ FPGAs Data sheet
* Revision change in one or more subcores
2018.2:
* Version 11.2 (Rev. 5)
* Bug Fix: Changed logic to transmit invalid headers during PMA_INIT assertion to ensure that link partner loses block sync.
* Bug Fix: Aurora TX,RX clocking helper blocks updated to match that of UltraScale GT Wizard IP.
* Bug Fix: Modified logic to assert GT RX Datapath Reset when Hard error occurs.
* Bug Fix: Fixed core generation issues when targeting the IP to QVIRTEXUPLUS and QZYNQUPLUS devices.
* Revision change in one or more subcores
2018.1:
* Version 11.2 (Rev. 4)
* Bug Fix: Fixed the default tie-off values for rxlpmen port as per INS_LOSS_NYQ and RX_EQ_MODE selection
* Other: Updated the initial value being driven in example design simulation top for PMA_INIT input
* Revision change in one or more subcores
2017.4:
* Version 11.2 (Rev. 3)
* Bug Fix: Fixed CDC warning for HLD_POLARITY_OUT signal.
* Revision change in one or more subcores
2017.3:
* Version 11.2 (Rev. 2)
* General: Fifo Generator version upgrade.
* General: Updated display values of RX_TERMINATION_PROG_VALUE for UltraScale+ devices to match Xilinx UltraScale Architecture Transceivers user guides
* Revision change in one or more subcores
2017.2:
* Version 11.2 (Rev. 1)
* Bug Fix: for multi-quad GTY based designs with line rate more than 16.375 gbps the reference clock locatons are added in XDC
* Other: UltraScale GT Wizard version upgrade.
2017.1:
* Version 11.2
* New Feature: US GT Wizard Instance can be brought out of Aurora IP for UltraScale devices
* Other: gt_powergood from US GT Wizard is made an output port on Aurora core when GT is inside Aurora IP
* Other: gt_powergood from US GT Wizard is brought to gt wrapper in example design when the GT is in example design, outside Aurora IP
* Revision change in one or more subcores
2016.4:
* Version 11.1 (Rev. 3)
* Revision change in one or more subcores
2016.3:
* Version 11.1 (Rev. 2)
* Feature Enhancement: Added Advanced RX GT Options selection in GUI for UltraScale devices
* Feature Enhancement: Added support for GTYE4 upto 25.7813Gbps line rates
* Feature Enhancement: Updated support for GTYE3 upto 25.7813Gbps line rates
* Revision change in one or more subcores
2016.2:
* Version 11.1 (Rev. 1)
* COMMON_CFG[6] attribute value updated for configurations with QPLL on GTHE2 Transceiver based devices
* Revision change in one or more subcores
2016.1:
* Version 11.1
* Improved Performance and Utilization for GTY designs in Framing mode
* Added feature to preview shared logic files when Shared logic in Example Design option is selected
* Removed the dependency on gtwiz_reset_rx_cdr_stable_out from GT channel to re-initialize the core for UltraScale Devices
* Added gt_rxusrclk_out optional port when Additional transceiver control and status ports option is enabled
* Revision change in one or more subcores
2015.4.2:
* Version 11.0 (Rev. 1)
* No changes
2015.4.1:
* Version 11.0 (Rev. 1)
* No changes
2015.4:
* Version 11.0 (Rev. 1)
* Added support for new speedgrades of XQ7K325T and XQ7K410T devices
* Added support for new speedgrades of XQ7Z030, XQ7Z045 and XQ7Z100 devices
* Revision change in one or more subcores
2015.3:
* Version 11.0
* Added support for GTY upto 25Gbps line rates
* One GTREFCLK input per quad is a requirement for line rates above 16.375Gbps for GTY
* CRC implementation is not backward compatible for line rates above 16.375Gbps for GTY
* UFC and USERK interfaces are not supported for line rates above 16.375Gbps for GTY
* Added support for XC7Z030SBV485 and XC7Z030ISBV485 devices
* UltraScale GT Wizard and FIFO subcore versions updated
* s_axi_user_k_tx_tready output gated with channel_up
* TXMASTERCHANNEL and RXMASTERCHANNEL selection updated for UltraScale Transceivers
* Added support for UltraScale+ devices
2015.2.1:
* Version 10.0 (Rev. 1)
* No changes
2015.2:
* Version 10.0 (Rev. 1)
* Added support for XQ7Z045RFG676, XQ7Z100RF1156 and XQ7VX690TRF1158 devices
2015.1:
* Version 10.0
* Added support for 7-series devices with FFV and FBV Pb-Free RoHs packages
* Max line rate support of 16.375G added for Ultrascale GTH devices
* Added support for Simplex Auto recovery
* Added txinhibit and pcsrsvdin optional transceiver control and status ports
* Both pma_init and reset_pb ports made asynchronous to the core; reset, tx_reset and rx_reset input ports removed
* Standard CC module made part of the IP, do_cc port removed
* Flow control axi ports grouped into AXI4 Stream interfaces
* Control and status ports are grouped as display interfaces
* Added support for single ended clocking option to INIT_CLK and GTREFCLK
* Added support for contiguous lane selection for Ultrascale devices
* CRC resource utilization optimized
* GT Reference Clocks, User Clock and Sync Clock ports updated with expected frequency values in IP-Integrator
* Line rate value restricted to 4 decimal digits for Ultrascale devices
* INIT clock frequency value restricted to 6 decimal digits
2014.4.1:
* Version 9.3 (Rev. 1)
* No changes
2014.4:
* Version 9.3 (Rev. 1)
* Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI, XC7K480TI, XC7Z030I, XC7Z035, XC7Z035I, XC7Z045I, XC7Z100I devices
* Minor update to XDC for board support
2014.3:
* Version 9.3
* Added support for XA7Z030 devices
* Ultrascale GT Wizard version updated
* Core resets separated for TX/RX_Simplex dataflow configuration
* AXI4-LITE protocol compliant GT DRP interface with optional ports added
* Per lane AXI4-LITE GT DRP interface supported for 7-series core
* Added support for user configurable DRP clock and INIT clock through IP GUI
* User selectable option enabled for GT DRP interface in IP-Integrator
* Added support for auto-propagate to INIT and DRP clock in IPI systems
* Addressed CPLL power down circuit requirement for 7 series Transceivers - refer AR
* Added support for Xilinx Evaluation platform boards
* XDCs compliant with updated timing constraining guidelines
* Differential INIT clock input added
AURORA+CHIP2CHIP内回环与外回环总结
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2024-04-29
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AURORA+CHIP2CHIP内回环与外回环总结 （162个子文件） 
aurora_64b66b_xczu15eg.dcp 1.14MB proc_sys_reset_0.dcp 23KB clk_wiz_0.dcp 13KB axi_chip2chip_master_top.sv 18KB master_top.sv 18KB axi_chip2chip_slave_top.sv 18KB slave_top.sv 17KB aurora_slv_top.sv 13KB aurora_example.sv 12KB aurora_top.sv 10KB top.sv 10KB aurora_core.sv 9KB tb_common.sv 8KB axi_chip2chip_xczu15eg_dut.sv 6KB axi_chip2chip_vu19p_dut.sv 6KB clk_gen.sv 3KB
aurora_64b66b_v12_0_changelog.txt 13KB aurora_64b66b_xczu15eg_sim_netlist.v 2.18MB fifo_generator_v13_2_rfs.v 584KB fifo_generator_v13_2_rfs.v 584KB fifo_generator_vlog_beh.v 442KB fifo_generator_vlog_beh.v 442KB aurora_64b66b_xczu15eg_gt_gtwizard_top.v 277KB aurora_64b66b_xczu15eg_gt_gtwizard_top.v 277KB aurora_64b66b_xczu15eg_gt_gtwizard_gtye4.v 275KB aurora_64b66b_xczu15eg_gt_gtwizard_gtye4.v 275KB gtwizard_ultrascale_v1_7_gtye4_channel.v 226KB gtwizard_ultrascale_v1_7_gtye4_channel.v 226KB aurora_64b66b_xczu15eg_gt_gtye4_channel_wrapper.v 108KB aurora_64b66b_xczu15eg_gt_gtye4_channel_wrapper.v 108KB aurora_64b66b_xczu15eg_wrapper.v 78KB aurora_64b66b_xczu15eg_cbcc_gtx_6466.v 57KB gtwizard_ultrascale_v1_7_gtye4_common.v 53KB gtwizard_ultrascale_v1_7_gthe4_cpll_cal_tx.v 39KB gtwizard_ultrascale_v1_7_gtye4_cpll_cal_tx.v 39KB gtwizard_ultrascale_v1_7_gtye4_cpll_cal_rx.v 36KB gtwizard_ultrascale_v1_7_gthe4_cpll_cal_rx.v 36KB aurora_64b66b_xczu15eg_multi_wrapper.v 36KB gtwizard_ultrascale_v1_7_gtwiz_reset.v 32KB aurora_64b66b_xczu15eg_gt_gtye4_common_wrapper.v 29KB aurora_64b66b_xczu15eg_gt.v 29KB m_c2c_traffic_chk.v 28KB s_c2c_traffic_chk.v 28KB aurora_64b66b_xczu15eg_gt.v 26KB aurora_64b66b_xczu15eg_core.v 25KB gtwizard_ultrascale_v1_7_gthe3_cpll_cal.v 25KB proc_sys_reset_0_sim_netlist.v 24KB aurora_64b66b_xczu15eg_cdc_sync.v 23KB s_c2c_traffic_gen.v 21KB m_c2c_traffic_gen.v 21KB aurora_64b66b_xczu15eg_support.v 19KB aurora_64b66b_xczu15eg_fifo_gen_master.v 15KB aurora_64b66b_xczu15eg_fifo_gen_slave.v 15KB aurora_64b66b_xczu15eg_channel_init_sm.v 15KB gtwizard_ultrascale_v1_7_gtye4_cpll_cal.v 14KB gtwizard_ultrascale_v1_7_gthe4_cpll_cal.v 14KB aurora_64b66b_xczu15eg_polarity_check.v 13KB aurora_64b66b_xczu15eg_lane_init_sm.v 13KB gtwizard_ultrascale_v1_7_gtwiz_userdata_tx.v 12KB gtwizard_ultrascale_v1_7_gtwiz_buffbypass_tx.v 12KB gtwizard_ultrascale_v1_7_gte4_drp_arb.v 12KB gtwizard_ultrascale_v1_7_gtwiz_buffbypass_rx.v 11KB aurora_64b66b_xczu15eg_support_reset_logic.v 11KB aurora_64b66b_xczu15eg_block_sync_sm.v 11KB aurora_64b66b_xczu15eg_common_reset_cbcc.v 11KB aurora_64b66b_xczu15eg_sym_dec.v 11KB aurora_64b66b_xczu15eg_aurora_lane.v 10KB aurora_64b66b_xczu15eg.v 10KB gtwizard_ultrascale_v1_7_gtwiz_userdata_rx.v 10KB aurora_64b66b_xczu15eg_standard_cc_module.v 9KB clk_wiz_0_sim_netlist.v 8KB aurora_64b66b_xczu15eg_sym_gen.v 8KB clk_wiz_0_clk_wiz.v 7KB aurora_64b66b_xczu15eg_ultrascale_rx_userclk.v 7KB aurora_64b66b_xczu15eg_ultrascale_tx_userclk.v 7KB gtwizard_ultrascale_v1_7_gthe3_cal_freqcnt.v 6KB gtwizard_ultrascale_v1_7_gthe4_cal_freqcnt.v 6KB gtwizard_ultrascale_v1_7_gtye4_cal_freqcnt.v 6KB gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v 6KB gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v 6KB aurora_64b66b_xczu15eg_tx_stream_control_sm.v 6KB aurora_64b66b_xczu15eg_width_conversion.v 6KB aurora_64b66b_xczu15eg_global_logic.v 6KB gtwizard_ultrascale_v1_7_gtwiz_userclk_tx.v 6KB gtwizard_ultrascale_v1_7_gtwiz_userclk_rx.v 6KB aurora_64b66b_xczu15eg_common_logic_cbcc.v 6KB aurora_64b66b_xczu15eg_gt_common_wrapper.v 6KB aurora_64b66b_xczu15eg_err_detect.v 5KB aurora_64b66b_xczu15eg_reset_logic.v 5KB aurora_64b66b_xczu15eg_tx_stream.v 5KB aurora_64b66b_xczu15eg_tx_stream_datapath.v 5KB aurora_64b66b_xczu15eg_ch_bond_code_gen.v 5KB aurora_64b66b_xczu15eg_clock_module.v 5KB aurora_64b66b_xczu15eg_64b66b_descrambler.v 5KB aurora_64b66b_xczu15eg_rx_stream_datapath.v 5KB aurora_64b66b_xczu15eg_64b66b_scrambler.v 4KB aurora_64b66b_xczu15eg_rx_stream.v 4KB aurora_64b66b_xczu15eg_channel_err_detect.v 4KB clk_wiz_0.v 4KB gtwizard_ultrascale_v1_7_reset_inv_sync.v 4KB共 162 条
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