Zynq-7000 EPP
Technical Reference
Manual
UG585 (v1.2) August 8, 2012
Zynq‐7000EPPTechnicalReferenceManual www.xilinx.com 2
UG585(v1.2)August8,2012
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RevisionHistory
The following table shows the revision history for this document. Change bars indicate the latest revisions.
Date Version Revision
04/08/12 1.0 Xilinx initial release.
Zynq‐7000EPPTechnicalReferenceManual www.xilinx.com 3
UG585(v1.2)August8,2012
06/25/12 1.1 Removed Chapter 30, Board Design (now part of UG933, Zynq-7000 EPP PCB Design and
Pin Planning Guide).
08/08/12 1.2 Added information about the
7z010 CLG225 device and references to section
2.4.4 MIO-at-a-Glance Table throughout document.
Added section headings
1.1.1 Block Diagram and 1.1.2 Documentation Resources, added sections 1.1.3 Notices
and TrustZone Capabilities, and clarified PS MIO I/Os in Chapter 1. Updated Tab le 2- 1 .
Changed 2.4.2 MIO-EMIO Connections heading to 2.4.2 IOP Interface Connections and
clarified first paragraph. Updated Tabl e 2-4. Added section 2.4.8 PS–PL Voltage Level
Shifter Enables and Tab le 2-7 , and updated Tabl e 2-13 PS MIO I/Os in Chapter 2. Added
note under Branch Prediction and Table 3- 4 in Chapter 3. Updated Table 4-1 in
Chapter 4. Added section 5.1.7 Read/Write Request Capability in Chapter 5. Updated
NAND MIO pin assignments and Table 6-6 in Chapter 6. Updated section
7.2 Functional Description in Chapter 7. Added section heading 10.1.1 Features and
added section 10.1.3 Notices in Chapter 10. Updated Parallel (SRAM/NOR) Interface
features list and added section 11.1.3 Notices in Chapter 11. Reorganized, clarified, and
expanded Chapter 12 to include programming models (added sections 12.1.4 Notices,
12.3 Programming Guide, and 12.5.2 MIO Programming). Added last note in section
13.3.4 Using ADMA in Chapter 13. Added Restrictions in Chapter 14. Clarified first
paragraph, added section 15.1.3 Notices, and clarified Figure 15-7 through
Figure 15-11 in Chapter 15. Added section 16.1.4 Notices in Chapter 16. Clarified
sections 17.2.5 SPI FIFOs, 17.2.6 SPI Clocks, and 17.2.7 SPI EMIO Considerations in
Chapter 17. Reorganized, clarified, and expanded Chapter 18 to include programming
models (added sections 18.1.4 Notices and 18.5.1 MIO Programming). Reorganized,
clarified, and expanded Chapter 19 to include programming models (added sections
19.1.4 Notices, 19.3 Programming Guide, and 19.5.1 MIO Programming). Updated
Table 22-2 and Tabl e 22-3 in Chapter 22. Added section
25.12.5 CPU_DIVISOR(ARM_CLK_CTRL[13:8]) in Chapter 25. Updated Table 26-4 in
Chapter 26. Clarified section 27.3 I/O Signals in Chapter 27. Added section
28.1.2 Notices in Chapter 28. Clarified Mapping Summary and updated
Tab l e 29-1 ,
Table 29-3, and Table 29 -5 in Chapter 29. Added section 30.1.3 Notices in Chapter 30.
Updated data sheet references in section A.3.1 Zynq-7000 EPP Documents of
Appendix A. Updated register database in sections B.3 Module Summary through
B.34 USB Controller (usb) in Appendix B.
Date Version Revision
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UG585(v1.2)August8,2012
TableofContents
RevisionHistory ....................................................................2
Chapter 1: Introduction
1.1 Overview ....................................................................21
1.1.1 BlockDiagram ............. ........................................... ...............22
1.1.2 D ocumentationResources ................... ..........
................................23
1.1.3 Notices ...................
..........................................................24
1.2 ProcessingSystem(PS)FeaturesandDescriptions ..................................25
1.2.1 Application Pr ocessorUnit(APU) ... ....................................................25
1.2.2 MemoryInterfaces ..........................................
.........................26
1.2.3 I/OPeripherals ........................
..............................................28
1.3 ProgrammableLogicFeaturesandDescriptions ....................................32
1.4 Interconn ectFeaturesandDescription......
......................................33
1.4.1 PSInterconnectBasedonAXIHighPerformanceDataPathSwitches..........................33
1.4.2 PS‐PLInterfaces .............
...................................... .. ................34
1.5 SystemSoftware ..............................................................35
Chapter 2: Signals,Interfaces,andPins
2.1 Introduction .............................................. ...................36
2.2 PowerPins..................................
.................................36
2.3 PSI/OPins ...............
....................................................38
2.4 MIO‐EMIO..............................................
.....................38
2.4.1 I/OPeripheral(IOP)InterfaceRouting ...................................................39
2.4.2 IOPInterfaceConnections ................ ............................
.................40
2.4.3 MIOPinAssignmentConsiderations ...............................
......................41
2.4.4 MIO‐at‐a‐GlanceTable .........................
.......................................43
2.4.5 MIOSignalRouting ..........
.........................................................44
2.4.6 DefaultLogicLevels .........................................
............... ..........44
2.4.7 MIOPinElectricalParameters ................ .......
............... ....................45
2.4.8 P S–PLVoltageLevelShifterEnables ...........
................................... .......46
2.5 PLAXIInterfaces ..............................................................46
2.6 PL–PSSignals....................................
.............................46
2.6.1 ClocksandResets....................................................................47
2.6.2 I nterruptSignals ........ .....................
........................................47
2.6.3 EventSignals ........ .
....................................... .................... ....48
2.6.4 IdleAXI,DDRUrgent/Arb,SRAMInterruptSignals ...............................
..........48
2.6.5 DMAReq/AckSignals ............. ..........................
..........................49
2.7 PLI/OPins ...................................................................49
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UG585(v1.2)August8,2012
Chapter 3: ApplicationProcessingUnit
3.1 Introduction .............................................. ...................51
3.1.1 BasicFunctionality ...................................................................51
3.1.2 System‐levelView ............. ..................
.....................................53
3.2 CortexA9Processors ..........................................................55
3.2.1 Summary...........................................................................55
3.2.2 C entralProcessingUnit(CPU)......................
....................................55
3.2.3 Level1Caches .............
..........................................................58
3.2.4 MemoryManagementUnit(MMU) .......................................
..............60
3.2.5 Interfaces ... ..................................
............... .......................63
3.2.6 NEON............
................................... ...............................64
3.2.7 PerformanceMonitoringUnit ..................................
........................65
3.3 SnoopControlUnit(SCU)....... ................................................65
3.3.1 Summary...........................................................................65
3.3.2 AddressFiltering .........................
....................................... .....66
3.3.3 SCUMasterPorts ....
................................................................66
3.4 L2‐Cache ..... .... ...........................................................66
3.4.1 Summary...........................................................................66
3.4.2 ExclusiveL2‐L1CacheConfiguration .............. ........
...............................70
3.4.3 CacheReplacementStrategy ..................
.........................................71
3.4.4 CacheLockdown .........
....................................... .....................71
3.4.5 EnablingandDisablingtheL2CacheController .. .................................
.........72
3.4.6 RAMAccessLatencyControl......................................
.....................73
3.4.7 StoreBufferOperation ............................
............... .....................73
3.4.8 OptimizationsBetweenCortex‐A9andL2Controller ........
............... ................74
3.4.9 Pre‐fetchingOperation................. .
............... ...............................75
3.4.10 ProgrammingModel....
...................................... .. .....................76
3.5 APUInterfaces ...............................................................77
3.5.1 PLCo‐processingInterfaces ............................................................77
3.5.2 I nterruptInterface ............... ......................
..............................80
3.6 SupportforTrustZoneWithintheAPU .................................... ........81
3.6.1 CPUSecurityTransition ........... .. ........................................... .......81
3.6.2 CP15RegisterAccessControl ................................
..........................82
3.6.3 MMUSecurity ................ ........
....................................... ........83
3.6.4 L‐1CacheSecurity .
...................................................................83
3.6.5 SecurityExceptionControl ................................
.............................84
3.6.6 CPUDebugTrustZoneAccessControl ..................
..................................84
3.6.7 SCURegisterAccessControl .............
............... ...............................84
3.6.8 TrustZoneSupportintheL2
Cache .................................... .. ................84
3.7 ApplicationProcessingUnit(APU)Reset ..........................................85
3.7.1 ResetFunctionality ............................ .......................................85
3.7.2 APUStateAfterReset............... ................
..................................86
3.8 PowerConsiderations .........................................................86
3.8.1 I ntroduction ......................... ........................................... ....86
3.8.2 StandbyMode ..... .......................
...........................................87
3.8.3 DynamicClockGatingintheL2Controller ..
..............................................87
