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The SPARC Architecture Manual Version 8
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SPARC is a CPU instruction set architecture (ISA), derived from a reduced instruction set computer (RISC) lineage. As an architecture, SPARC allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications, including scientific/engineering, programming, real-time, and commercial.
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SPARC International Inc. 535 Middlefield Road, Suite 210
Menlo Park, CA 94025 415-321-8692
SPARC International, Inc.
The SPARC Architecture Manual
Version 8
Revision SAV080SI9308
SPARC is a registered trademark of SPARC International, Inc.
The SPARC logo is a registered trademark of SPARC International, Inc.
UNIX and OPEN LOOK are registered trademarks of UNIX System Labora-
tories, Inc.
Copyright 1991,1992 SPARC International, Inc. Printed in U.S.A.
All rights reserved.
No part of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means, electronic, mechanical, photocopying,
recording or otherwise, without the prior permission of the copyright owners.
Restricted rights legend: use, duplication, or disclosure by the U.S. government
is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 52.227-7013 and in
similar clauses in the FAR and NASA FAR Supplement.
The SPARC Architecture Manual
Version 8
Revision SAV080SI9308
1
Introduction
This document specifies Version 8 of the Scalable Processor ARChitecture,
or SPARC.
1.1. SPARC Attributes SPARC is a CPU instruction set architecture (ISA), derived from a reduced
instruction set computer (RISC) lineage. As an architecture, SPARC allows for a
spectrum of chip and system implementations at a variety of price/performance
points for a range of applications, including scientific/engineering, programming,
real-time, and commercial.
Design Goals SPARC was designed as a target for optimizing compilers and easily pipelined
hardware implementations. SPARC implementations provide exceptionally high
execution rates and short time-to-market development schedules.
Register Windows SPARC, formulated at Sun Microsystems in 1985, is based on the RISC I & II
designs engineered at the University of California at Berkeley from 1980 through
1982. the SPARC “register window” architecture, pioneered in UC Berkeley
designs, allows for straightforward, high-performance compilers and a significant
reduction in memory load/store instructions over other RISCs, particularly for
large application programs.
For languages such as C++, where object-oriented programming is dominant,
register windows result in an even greater reduction in instructions executed.
Note that supervisor software, not user programs, manages the register windows.
A supervisor can save a minimum number of registers (approximately 24) at the
time of a context switch, thereby optimizing context switch latency.
One difference between SPARC and the Berkeley RISC I & II is that SPARC
provides greater flexibility to a compiler in its assignment of registers to program
variables. SPARC is more flexible because register window management is not
tied to procedure call and return (CALL and JMPL) instructions, as it is on the
Berkeley machines. Instead, separate instructions (SAVE and RESTORE) pro-
vide register window management.
1
SPARC International, Inc.
2 The SPARC Architecture Manual: Version 8
1.2. SPARC System
Components
The architecture allows for a spectrum of input/output (I/O), memory manage-
ment unit (MMU), and cache system sub-architectures. SPARC assumes that
these elements are optimally defined by the specific requirements of particular
systems. Note that they are invisible to nearly all user application programs and
the interfaces to them can be limited to localized modules in an associated
operating system.
Reference MMU The SPARC ISA does not mandate that a single MMU design be used for all sys-
tem implementations. Rather, designers are free to use the MMU that is most
appropriate for their application — or no MMU at all, if they wish. A SPARC
“Reference MMU” has been specified, which is appropriate for a wide range of
applications. See Appendix H, “SPARC Reference MMU Architecture,” for
more information.
Supervisor Software SPARC does not assume all implementations must execute identical supervisor
software. Thus, certain supervisor-visible traits of an implementation can be
tailored to the requirements of the system. For example, SPARC allows for
implementations with different instruction concurrency and different exception
trap hardware.
Memory Model
A standard memory model called Total Store Ordering (TSO) is defined for
SPARC. The model applies both to uniprocessors and to shared-memory mul-
tiprocessors. The memory model guarantees that the stores, FLUSHes, and
atomic load-stores of all processors are executed by memory serially in an order
that conforms to the order in which the instructions were issued by processors.
All SPARC implementations must support TSO.
An additional model called Partial Store Ordering (PSO) is defined, which allows
higher-performance memory systems to be built.
Machines (including all early SPARC-based systems) that implement Strong
Consistency (also known as Strong Ordering) automatically satisfy both TSO and
PSO. Machines that implement TSO automatically satisfy PSO.
1.3. SPARC Compliance
Definitions
An important SPARC International Compatibility and Compliance Committee
function is to establish and publish SPARC Compliance Definitions (SCDs) and
migration guidelines between successive definitions. SCD use accelerates
development of binary-compatible SPARC/UNIX systems and software for both
system vendors and ISV members. SPARC binaries executed in user mode
should behave identically on all SPARC systems when those systems are running
an operating system known to provide a standard execution environment.
AT&T and SPARC International have developed a standard Application Binary
Interface (ABI) for the development of SPARC application code. Software con-
forming to this specification will produce the same results on every SPARC
ABI-compliant system, enabling the distribution of ‘‘shrink-wrapped’’ SPARC
software. Although different SPARC systems will execute programs at different
rates, they will generate the same results.
SPARC International, Inc.
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