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Date Printed: April 6, 2004 Page 1

Overview of the

SPARC Architecture

Harry Porter

Computer Science Department

Portland State University

Abstract

This document provides an overview of the SPARC architecture and instruction set.

Only a portion of the architecture is covered. The view presented here is simplified

to provide an abstraction that should be adequate for user-level programming.

Memory

Main memory is byte addressable. Addresses are 4 bytes (i.e., 32 bits), allowing for up to 4

gigabytes of memory to be addressed.

Every instruction is 4 bytes (i.e., 32 bits) long. Instructions must be word aligned. That is, the their

addresses must be divisible by 4.

Bytes, Halfwords, Words, and Doublewords

Data is manipulated in 1, 2, 4, and 8 byte units called bytes, halfwords, words, and doublewords.

number number required aligned address

of bytes of bits alignment in binary

byte 1 8 none (any)

half 2 16 2 -----------0

word 4 32 4 ----------00

double 8 64 8 ---------000

Date Printed: April 6, 2004 Page 2

The bits within a word are numbered from 0 (least significant) to 31 (most significant).

byte:

7 0

half (2 bytes):

15 0

word (4 bytes):

31 0

| | |

double (8 bytes):

63 0

| | | | | | |

Alignment

Halfword, word, and doubleword data must be aligned in memory. For example, a 4 byte word

value must be placed at an address that is divisible by 4, and a doubleword must be placed at an

address that is divisible by 8. The load and store instructions will cause error exceptions if an

attempt is made to move a halfword, word, or doubleword quantity to/from an address that is not

properly aligned.

Big Endian

The SPARC architecture is “Big Endian,”!meaning that when a word-sized quantity is stored in 4

bytes of memory, the most significant byte is stored in the first byte (i.e., lowest numbered address)

and the least significant byte is stored in the last byte (i.e., the byte with the greatest address). In

other words, if a word is stored at address x, the most significant byte will be stored in byte x and

the least significant byte will be stored in address x+3.

Some other (non-SPARC) computers use “Little Endian” order, in which the least significant byte

is stored in the lowest numbered address.

Binary, Decimal, and Hex Notation

An integer may be represented many ways. Normally, we represent integers in decimal using 10

numeral symbols (0, 1, 2, 3, 4, 5, 6, 7, 8, and 9). The position (i.e., “place”) of each digit in the

representation is significant. The place values are: ones, tens, hundreds, thousands, and so on.

Integers represented in binary use only two numeral symbols (0 and 1). The bit in each place is

multiplied by a power of 2. Thus, the place values are: 1's, 2's, 4's, 8's, 16's, and so on.

Integers represented in hex use sixteen digits (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F). The

hex digit in each place is multiplied by a power of 16. Thus, the place values are: 1's, 16's, 256's,

4096's, 65536's, and so on.

Date Printed: April 6, 2004 Page 5

The range of values that can be represented depends on the number of bits being used:

byte half word

total 2

number = 256 = 65,536 = 4,294,967,296

of values = 64K = 4G

largest 2

-1 2

-1

positive = 127 = 32,767 = 2,147,483,647

number = 32K-1 = 2G-1

most -2

-2

negative = -128 = -32,768 = -2,147,483,648

number = -32K = -2G

Load Store Architecture

The SPARC uses a “load-store” architecture. Operations (such as arithmetic and logical

functions) can only be performed on data stored in registers. It is necessary to move the data from

memory to registers (load it) and back to memory (store it) with separate instructions. The

instructions in the following example are not exactly SPARC instructions, but they give you the

idea of load-store architectures. Here, “x,” “y,” and “z” are the names of some memory

locations and “r1,” “r2,” and “r3” are the names of registers.

load x,r1

load y,r2

add r1,r2,r3

store r3,z

The first instruction moves data from memory into register “r1.” The second instructions moves a

number into register “r2.” The third instruction adds the values in “r1” and “r2,” placing the

result into register “r3.” The final instructions moves data from register “r3” back to main

memory.

Each SPARC instruction either does a memory access or does a computation. The idea is that each

instruction will be executed in one machine cycle. (Actually, in one machine cycle on average; due

to pipelining—i.e., instruction overlapping—the execution of each instruction will be spread over

several cycles.)

This architecture works best if all (or most all) the data can be kept in registers. Toward this end,

the SPARC provides a large number of registers. Accessing memory slows microprocessors down

and the goal is to minimize memory accessing by keeping all relevant data in registers.

Integer Registers

Each running process may access 32 “integer” registers. (“Floating-point” register are discussed

later.) Each integer register contains one word (32 bits) of data. Actually, each integer register has

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