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数字密码锁verilog设计+仿真+上板验证
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2022-12-12
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数字密码锁verilog-仿真-上板验证.rar （98个子文件） 
数字密码锁verilog-仿真-上板验证 
代做FPGA-QQ778132974.txt 0B key数字密码锁verilog-仿真-上板验证 ff src project_1.sim sim_1 behav xsim 
top_lock_vlg_tst_behav.wdb 27.39MB webtalk_18440.backup.log 951B xsim.dir xil_defaultlib key_board.sdb 5KB top_lock_vlg_tst.sdb 2KB key_function.sdb 5KB lock_ctrl.sdb 11KB display.sdb 8KB xil_defaultlib.rlx 864B top_lock.sdb 4KB glbl.sdb 4KB top_lock_vlg_tst_behav xsimcrash.log 0B TempBreakPointFile.txt 29B xsim.dbg 20KB xsim.xdbg 4KB obj xsim_1.win64.obj 5KB xsim_0.win64.obj 54KB xsim_1.c 7KB
xsimk.exe 104KB xsimkernel.log 343B xsim.type 24B xsim.mem 7KB xsim.rtti 190B xsimSettings.ini 1KB webtalk 
usage_statistics_ext_xsim.html 3KB usage_statistics_ext_xsim.xml 3KB .xsim_webtallk.info 64B Compile_Options.txt 266B xsim.svtype 39B xsim.reloc 4KB xsim.rlx 877B xvlog.log 1KB webtalk_1860.backup.jou 886B xvlog.pb 2KB top_lock_vlg_tst_vlog.prj 352B webtalk_6380.backup.log 950B webtalk_1860.backup.log 955B webtalk.jou 887B simulate.bat 960B compile.log 1KB xsim.ini 40B top_lock_vlg_tst.tcl 460B elaborate.bat 1KB glbl.v 1KB webtalk_18440.backup.jou 882B elaborate.log 3KB simulate.log 50B xelab.pb 5KB .Xil Webtalk-6380-LAPTOP-UBFVUKT0 webtalk Webtalk-15624-LAPTOP-UBFVUKT0 webtalk Webtalk-1860-LAPTOP-UBFVUKT0 webtalk Webtalk-18440-LAPTOP-UBFVUKT0 webtalk webtalk.log 956B webtalk_6380.backup.jou 881B compile.bat 850B project_1.ip_user_files README.txt 130B project_1.hw project_1.lpr 290B project_1.xpr 10KB vivado.log 13KB pro_create.tcl 385B display.v 4KB timescale.v 914B 上板验证过.txt 0B
Cache_-1d3e417ce995b4db..jpg 50KB key_function.v 2KB vivado_pid9172.str 36KB project_1.runs synth_1 ISEWrap.js 8KB .vivado.end.rst 0B runme.sh 1KB vivado.pb 51KB top_lock.tcl 2KB runme.bat 229B ISEWrap.sh 2KB vivado.jou 705B htr.txt 393B .vivado.begin.rst 217B project.wdf 4KB .Vivado_Synthesis.queue.rst 0B top_lock_utilization_synth.rpt 7KB top_lock.vds 29KB runme.log 30KB top_lock_utilization_synth.pb 242B rundef.js 1KB .Xil gen_run.xml 3KB top_lock.dcp 17KB __synthesis_is_complete__ 0B .jobs vrs_config_3.xml 382B vrs_config_1.xml 381B vrs_config_2.xml 382B project_1.cache wt webtalk_pa.xml 4KB project.wpc 61B gui_handlers.wdf 3KB java_command_handlers.wdf 1KB synthesis.wdf 5KB xsim.wdf 256B synthesis_details.wdf 100B compile_simlib questa xcelium ies modelsim vcs riviera activehdl lock_ctrl.v 6KB vivado.jou 1KB top_lock.v 2KB key_board.v 4KB .Xil Vivado-9172-LAPTOP-UBFVUKT0 auto.bat 274B sim timescale.v 908B prj 
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