The key functional elements are described next, and are
shown in the block diagram:
Image Sensing Elements: The CCD photo-sensitive
elements are made up of contiguous pixels with no voids
or inactive areas. In addition to sensing light, these
elements are used to shift image charge vertically. The
full frame architecture requires that the device be
mechanically shuttered during readout.
Frontside Illumination: In frontside illumination sensors,
incident photons pass through
the
overlaying
polycrystalline silicon gate structures,
and
generate
electron-hole pairs in the CCD during the integration
period. The photogenerated electrons are then
collected in the depletion regions in the photosites,
while the holes migrate to substrate ground. The
amount of charge accumulated in each photosite varies
linearily as a function of the incident illumination level and
the integration period.
Vertical Charge Shifting: The architecture of the
CCD6161 provides video information as a sequential
readout of 4096 lines, each containing 4096
photosensitive elements (in 1x1 mode, using a single
output). At the end of the integration period, the ΦV
1
,
ΦV
2
, and ΦV
3
gates are clocked to transfer charge
vertically through the CCD array and t
o
the
horizontal
readout register. Vertical columns are separated by
channel stop regions to confine charge horizontally. The
Vertical Transfer Gate
(ΦVTG)
is
the final array gate
before charge is transferred to the serial horizontal shift
registers. For simplified operation ΦVTG may be tied to
ΦV
3.
The imaging area is electrically divided into four
quadrants. Each
2048 x 2048 segment may be clocked
independently or combined as required. Horizontal serial
registers along the top and bottom permit simultaneous
readout of the upper and lower halves. The CCD6161
also may be clocked such that the full array is read out of
either the Upper or the Lower serial registers.
Horizontal Charge Shifting: ΦH
1
, ΦH
2
, and ΦH
3
are
polysilicon gates used to transfer charge horizontally to
the output amplifiers. The pixels in the horizontal
registers are twice the size of the photosites to allow
vertical charge binning, and a summing well is also
provided to support horizontal charge binning. The array
can be read out normally at 4k(H) x 4k(V) full resolution,
as a 4k(H) x 2k(V), or 2k(H) x 2k(V). The horizontal
shift registers are bi- directional so that the image
frame may be read out through a single, or two
amplifiers per serial register.
The transfer of charge into the horizontal registers
follows the vertical charge transport sequence. These
registers contain 18 additional register cells between the
first pixel of each line and the output amplifier. (Note that
the summing gate is part of the last prescan pixel.) The
output of these pixels contains no signals and may be
used as a dark level reference.
The last clocked gate in the Horizontal registers, ΦSG,
can be used to combine the signal charge of the pixels in
the horizontal shift registers. This gate requires its own
clock, which may be tied to ΦH
1
for normal full
resolution readout. The output
video
is
available
following the High to Low transition of ΦTG.
After the pixel has been sampled, the reset transistor,
clocked appropriately with ΦR, resets the sense node
potential to the level set by VRD.
Output Amplifier: The CCD6161 has a low noise
output amplifier at each end of the horizontal shift
registers for a total of four output ports. The single-
stage amplifier design has been optimized for low
readout noise. Signal charge packets are serially
clocked to a pre-charged capacitor, the sense node,
whose potential changes linearly in response to the
number of electrons delivered. This potential is applied to
the input gate of an NMOS amplifier producing a signal
at the output V
out
pin. The capacitor is reset with ΦR to
a pre-charge level prior to the arrival of the next charge
packet (except when horizontal binning is performed).
It is reset by use of the
reset
MOSFET.
The output
amplifier drain is tied
to
VDD. The source is
connected to an external load resistor to ground. The
voltage change at the source constitutes the video output
from the device.
Multi-Pinned Phase: MPP is a CCD technology
which significantly reduces the dark current generation
rate. CCDs are endowed with this capability by the
addition of an ion implant step during the semiconductor
manufacturing process.
This implant creates a built-in potential barrier in each
pixel, which allows charge integration to be performed
with all of the vertical clocks biased at their Low levels
(-8V). Under these conditions, the surface potential of
the CCD is pinned at 0V, and the holes released by the
neighboring p+ channel stops recombine with the
electrons that are generated by surface defects which
effectively neutralize the surface dark current.
While MPP operation significantly reduces the dark
current of the CCD, a drawback of the MPP mode is
reduced full well capacity. The potential barrier created
by MPP implant does not hold as much charge as the
normal buried channel operating mode which stores
charge under one of the vertical gates biased High during
integration. The CCD6161 fabrication process has been
optimized to maximize the charge capacity in MPP mode.