ES8388
ES8388 User Guide
2011-06-17
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1 ES8388 BLOCK DIAGRAM ..............................................................................................................................................................................................................................................3
2 RECOMMENDED OPERATING CONDITION................................................................................................................................................................................................................4
3 TYPICAL APPLICATION CIRCUIT ..................................................................................................................................................................................................................................5
4 I2C / SPI INTERFACE ........................................................................................................................................................................................................................................................6
5 DIGITAL AUDIO INTERFACE...........................................................................................................................................................................................................................................6
5.1 MASTER AND SLAVE MODE OPREATION ...........................................................................................................................................................................................................................7
5.2 MCLK / LRCK RATIO AND MCLK / SCLK RATIO ...........................................................................................................................................................................................................8
5.3 FOUR DIGITAL AUDIO FORMATS.......................................................................................................................................................................................................................................9
6 CHIP CONTROL AND POWER MANAGEMENT REGISTER....................................................................................................................................................................................11
7 ANALOG INPUT SIGNAL PATH ....................................................................................................................................................................................................................................12
7.1 THE ANALOG INPUT SIGNAL PATHS AND THE CONTROL REGISTER...................................................................................................................................................................................12
7.2 SINGLE-ENDED MICROPHONE INPUT ...............................................................................................................................................................................................................................14
7.3 PESUDO-DIFFERENTIAL MICROPHONE INPUT...................................................................................................................................................................................................................14
7.4 FULLY-DIFFERENTIAL MICROPHONE INPUT.....................................................................................................................................................................................................................14
8 ADC FOR RECORDING ..................................................................................................................................................................................................................................................15
8.1 THE ADC BLOCK DIAGRAM.............................................................................................................................................................................................................................................15
8.2 THE ADC CONTROL REGISTERS .....................................................................................................................................................................................................................................15
8.3 AUTOMATIC LEVEL CONTROL (ALC).............................................................................................................................................................................................................................16
8.3.1 CONTROL FIELDS................................................................................................................................................................................................................................................17
8.3.2 Recommended Settings for ALC.........................................................................................................................................................................................................................18
8.4 MICROPHONE INPUT CIRCUIT AND THE SAMPLE CODE FOR RECORDING ...........................................................................................................................................................................19
8.4.1 Fully-Differential Microphone input circuit and sample code...........................................................................................................................................................................19
8.4.2 Pseudo-Differential Microphone input circuit and sample code......................................................................................................................................................................20
8.4.3 Single ended Microphone input circuit and sample code................................................................................................................................................................................21
9 OUTPUT SIGNAL PATH..................................................................................................................................................................................................................................................21
9.1 THE OUTPUT SIGNAL PATHS AND THE CONTROL REGISTER...........................................................................................................................................................................................22
9.2 THE DAC CONTROL REGISTER .......................................................................................................................................................................................................................................24
9.3 EQUALIZER AND STEREO ENHANCEMENT .......................................................................................................................................................................................................................24
10 REGISTER CONFIGURATION SEQUENCE FOR ES8388.......................................................................................................................................................................................25
10.1 THE SEQUENCE FOR START UP CODEC.............................................................................................................................................................................................................................25
10.2 THE SEQUENCE FOR START UP RECORDING .....................................................................................................................................................................................................................26
10.3 THE SEQUENCE FOR START UP PLAY BACK MODE............................................................................................................................................................................................................26
10.4 THE SEQUENCE FOR START UP BYPASS MODE..................................................................................................................................................................................................................27
10.5 POWER DOWN SEQUENCE (TO STANDBY MODE)............................................................................................................................................................................................................27
10.6 RESUME FROM STANDBY MODE SEQUENCE.....................................................................................................................................................................................................................28