ARM
®
and Thumb
®
-2 Instruction Set
Quick Reference Card
Key to Tables
Rm {, <opsh>} See Table Register, optionally shifted by constant
<Operand2> See Table Flexible Operand 2. Shift and rotate are only available as part of Operand2. <reglist> A comma-separated list of registers, enclosed in braces { and }.
<fields> See Table PSR fields. <reglist-PC> As <reglist>, must not include the PC.
<PSR> Either CPSR (Current Processor Status Register) or SPSR (Saved Processor Status Register) <reglist+PC> As <reglist>, including the PC.
C*, V* Flag is unpredictable in Architecture v4 and earlier, unchanged in Architecture v5 and later. +/- + or –. (+ may be omitted.)
<Rs|sh> Can be Rs or an immediate shift value. The values allowed for each shift type are the same as those § See Table ARM architecture versions.
shown in Table Register, optionally shifted by constant. <iflags> Interrupt flags. One or more of a, i, f (abort, interrupt, fast interrupt).
x,y B meaning half-register [15:0], or T meaning [31:16]. <p_mode> See Table Processor Modes
<imm8m> ARM: a 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits. SPm SP for the processor mode specified by <p_mode>
Thumb: a 32-bit constant, formed by left-shifting an 8-bit value by any number of bits, or a bit <lsb> Least significant bit of bitfield.
pattern of one of the forms 0xXYXYXYXY, 0x00XY00XY or 0xXY00XY00. <width> Width of bitfield. <width> + <lsb> must be <= 32.
<prefix> See Table Prefixes for Parallel instructions {X} RsX is Rs rotated 16 bits if X present. Otherwise, RsX is Rs.
{IA|IB|DA|DB} Increment After, Increment Before, Decrement After, or Decrement Before. {!} Updates base register after data transfer if ! present (pre-indexed).
IB and DA are not available in Thumb state. If omitted, defaults to IA. {S} Updates condition flags if S present.
<size> B, SB, H, or SH, meaning Byte, Signed Byte, Halfword, and Signed Halfword respectively. {T} User mode privilege if T present.
SB and SH are not available in STR instructions. {R} Rounds result to nearest if R present, otherwise truncates result.
Operation § Assembler S updates Action Notes
Add Add ADD{S} Rd, Rn, <Operand2> N Z C V Rd := Rn + Operand2 N
with carry ADC{S} Rd, Rn, <Operand2> N Z C V Rd := Rn + Operand2 + Carry N
wide T2 ADD Rd, Rn, #<imm12> Rd := Rn + imm12, imm12 range 0-4095 T, P
saturating 5E QADD Rd, Rm, Rn Rd := SAT(Rm + Rn) Q
double saturating 5E QDADD Rd, Rm, Rn Rd := SAT(Rm + SAT(Rn * 2)) Q
Subtract Subtract SUB{S} Rd, Rn, <Operand2> N Z C V Rd := Rn – Operand2 N
with carry SBC{S} Rd, Rn, <Operand2> N Z C V Rd := Rn – Operand2 – NOT(Carry) N
wide T2 SUB Rd, Rn, #<imm12> N Z C V Rd := Rn – imm12, imm12 range 0-4095 T, P
reverse subtract RSB{S} Rd, Rn, <Operand2> N Z C V Rd := Operand2 – Rn N
reverse subtract with carry RSC{S} Rd, Rn, <Operand2> N Z C V Rd := Operand2 – Rn – NOT(Carry) A
saturating 5E QSUB Rd, Rm, Rn Rd := SAT(Rm – Rn) Q
double saturating 5E QDSUB Rd, Rm, Rn Rd := SAT(Rm – SAT(Rn * 2)) Q
Exception return without stack SUBS PC, LR, #<imm8> PC = LR – imm8, CPSR = SPSR(current mode), imm8 range 0-255. T
Parallel
arithmetic
Halfword-wise addition 6 <prefix>ADD16 Rd, Rn, Rm Rd[31:16] := Rn[31:16] + Rm[31:16], Rd[15:0] := Rn[15:0] + Rm[15:0] G
Halfword-wise subtraction 6 <prefix>SUB16 Rd, Rn, Rm Rd[31:16] := Rn[31:16] – Rm[31:16], Rd[15:0] := Rn[15:0] – Rm[15:0] G
Byte-wise addition 6 <prefix>ADD8 Rd, Rn, Rm Rd[31:24] := Rn[31:24] + Rm[31:24], Rd[23:16] := Rn[23:16] + Rm[23:16],
Rd[15:8] := Rn[15:8] + Rm[15:8], Rd[7:0] := Rn[7:0] + Rm[7:0]
G
Byte-wise subtraction 6 <prefix>SUB8 Rd, Rn, Rm Rd[31:24] := Rn[31:24] – Rm[31:24], Rd[23:16] := Rn[23:16] – Rm[23:16],
Rd[15:8] := Rn[15:8] – Rm[15:8], Rd[7:0] := Rn[7:0] – Rm[7:0]
G
Halfword-wise exchange, add, subtract 6 <prefix>ASX Rd, Rn, Rm Rd[31:16] := Rn[31:16] + Rm[15:0], Rd[15:0] := Rn[15:0] – Rm[31:16] G
Halfword-wise exchange, subtract, add 6 <prefix>SAX Rd, Rn, Rm Rd[31:16] := Rn[31:16] – Rm[15:0], Rd[15:0] := Rn[15:0] + Rm[31:16] G
Unsigned sum of absolute differences 6 USAD8 Rd, Rm, Rs Rd := Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])
+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])
and accumulate 6 USADA8 Rd, Rm, Rs, Rn Rd := Rn + Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])
+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])
Saturate Signed saturate word, right shift 6 SSAT Rd, #<sat>, Rm{, ASR <sh>} Rd := SignedSat((Rm ASR sh), sat). <sat> range 0-31, <sh> range 1-32. Q
Signed saturate word, left shift 6 SSAT Rd, #<sat>, Rm{, LSL <sh>} Rd := SignedSat((Rm LSL sh), sat). <sat> range 0-31, <sh> range 0-31. Q
Signed saturate two halfwords 6 SSAT16 Rd, #<sat>, Rm Rd[31:16] := SignedSat(Rm[31:16], sat),
Rd[15:0] := SignedSat(Rm[15:0], sat). <sat> range 0-15.
Q
Unsigned saturate word, right shift 6 USAT Rd, #<sat>, Rm{, ASR <sh>} Rd := UnsignedSat((Rm ASR sh), sat). <sat> range 0-31, <sh> range 1-32. Q
Unsigned saturate word, left shift 6 USAT Rd, #<sat>, Rm{, LSL <sh>} Rd := UnsignedSat((Rm LSL sh), sat). <sat> range 0-31, <sh> range 0-31. Q
Unsigned saturate two halfwords 6 USAT16 Rd, #<sat>, Rm Rd[31:16] := UnsignedSat(Rm[31:16], sat),
Rd[15:0] := UnsignedSat(Rm[15:0], sat). <sat> range 0-15.
Q
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