SAMSUNG-K7D161874B.pdf

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 1 -

Jan. 2005

K7D161874B

K7D163674B

Document Title

16M DDR SYNCHRONOUS SRAM

Revision History

Change JTAG DC OPERATING CONDITONS/AC TEST CONDITIONS

-to support 1.8~2.5V V

Change DC CHARACTERISTICS (Stop Clock Standby Current)

-I

-

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 2 -

Jan. 2005

K7D161874B

K7D163674B

ORDERING INFORMATION

Maximum

Frequency

K7D163674B-HC37

K7D161874B-HC33 333MHz

K7D161874B-HC30 300MHz

K7D161874B-HC27 275MHz

GENERAL DESCRIPTION

Single differential HSTL level clock, K and K

are used to initiate the read/write operation and all internal operations are self-timed. At

the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after

FEATURES

DD/1.5V VDDQ.(1.9V max VDDQ)

• HSTL Input and Outputs.

• Interleved and Linear Burst mode support

• Bypass Operation Support

• JTAG Boundary Scan (subset of IEEE std. 1149.1)

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 3 -

Jan. 2005

K7D161874B

K7D163674B

B

B

B

Data In

Advance

Control

Clock

Synchronous

Buffer

Internal

Clock

Output

Select

&

R/W

Output

2:1

MUX

SA[0:18]( or SA[0:19])

(1Mx18)

Rev 1.1

512Kx36 & 1Mx18 SRAM

- 4 -

Jan. 2005

K7D161874B

K7D163674B