JEDEC
PUBLICATION
Reliability Qualification of
Semiconductor Devices Based on
Physics of Failure Risk and
Opportunity Assessment
JEP148B
(Revision of JEP148A, December 2004)
JANUARY 2014, Reaffirmed September 2019
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
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JEDEC Publication No. 148B
-i-
RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES
BASED ON PHYSICS OF FAILURE AND RISK AND OPPORTUNITY ASSESSMENT
Contents
Page
Introduction ............................................................................................................................................. ii
1 Scope ......................................................................................................................................... 1
2 References ................................................................................................................................. 1
3 Terms and definitions ................................................................................................................. 2
4 Planning for quality and qualification: situation, approach and procedure ................................ 3
4.1 Application requirements............................................................................................................ 3
4.2 Qualification concepts ................................................................................................................ 3
4.3 The Physics-of-Failure concept ................................................................................................. 4
4.4 The systematic procedure: the Risk & Opportunity Assessment Process ................................. 5
4.5 Risk and opportunity assessment .............................................................................................. 8
4.6 Advance quality planning and qualification ................................................................................ 8
4.7 Guide through the process (How to use the WKM) ................................................................. 11
5 Reliability evaluation of integrated circuits, the methodology .................................................. 13
5.1 Reliability: the stability of product properties under stresses of use ........................................ 13
5.2 Reliability requirements and evaluation concept ..................................................................... 15
5.3 Applicability of models to complex products ............................................................................ 19
5.4 Basic reliability test scheme ..................................................................................................... 19
5.5 Statistical model distributions and the choice of sample sizes ................................................ 19
Annex A Examples of application of the Risk and Opportunity Assessment Process (ROAP) .......... 21
Annex B Other pertinent JEDEC documents and publications ........................................................... 29
Annex C Differences between Revisions ............................................................................................ 30
JEDEC Publication No. 148B
-ii-
Introduction
The penetration of semiconductor products into an increasing variety of application segments together
with the economic forces of cost and time-to-market require efficient qualification concepts. This
requirement influences the organization of the qualification process in conjunction with the development /
innovation process as well as the qualification methodology. Proactive practices such as advance quality
planning, "incremental qualification" and confirmation during development have to be practiced in order to
meet time to market goals. Results of theses activities including the use of further available knowledge
will be the basis for the qualification as evidence for the readiness of the product for the market.
These aspects are considered here by a straightforward approach to qualification being part and result of
careful development work.
Semiconductor devices specialize to application segments
The different application segments drive the increase and specialization of functionality, and also require
optimum solutions for economic integration of components into their systems, their application conditions
and application times. This is achieved by
- specific technological adaptation of the product construction (chip internal construction, package or
module design) frequently associated with new materials and new or modified technologies;
- use of products of mature designs and technologies by extending the knowledge about their
applicability in more demanding applications.
Time-to-market requires efficient quality planning and confirmation
Shortening time to-market period forces one to consider
- integration of qualification into the innovation process with early start of the qualification activities
replacing qualification as a separate and sequential activity,
- effective use of knowledge, i.e., applying existing results for qualification,
- compatibility with simultaneous engineering practices.
Reliability qualification will refer to physics-of-failure knowledge
As a consequence, the practices of qualifying products for reliability are changing
- from reactive activities at the end of a development cycle applying uniform and predefined stress
testing with generic qualification plans
- to measures deliberately integrated into the development cycle making proactive use of stricter
physics-of-failure based testing with respect to the product construction and the use conditions of the
application segment
- to approaches to measure the robustness with respect to well specified application conditions.
The approach taken is to:
• apply a systematic procedure which enables concentration on those product properties with respect
to product construction and application conditions which really need to be qualified
(part I),
• arrange the qualification methodology to correspond to the relationships between designs;
technology, manufacturing and product life phases at use conditions (part II).
JEDEC Publication No. 148B
Page 1
RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES
BASED ON PHYSICS OF FAILURE AND RISK AND OPPORTUNITY ASSESSMENT
(From JEDEC Board Ballot JCB-08-63, and JCB-13-58, formulated under the cognizance of the JC-14.3
Subcommittee on Silicon Devices Reliability Qualification and Monitoring.)
1 Scope
The purpose of this procedure provides a consistent frame work for reliability qualification using the
Physics-of-Failure (PoF) concept, which
− is flexible with respect to the requirements of the intended application and market,
− makes optimum use of the supplier’s advance quality planning and demonstration results gained during
design and development and applicable knowledge based on design and technology similarities.
Planning quality and reliability in advance and gaining reliability results with the progress of a design and
development process is efficiently supported by a systematic procedure for risk and opportunity
assessment.
The qualification concept is based on customer - supplier partnership in order to achieve optimized
efforts. The methodology applies to the reliability qualification of semiconductor devices and the
processes for their development and manufacturing.
2 References (informative)
[1] M. Pecht, A. Dasgupta, Physics of Failure: An Approach to Reliable Product Development, IRW Final
Report 95.
[2] K. Upadhyayula, A. Dasgupta, Physics-of-Failure Guidelines for Accelerating Qualification of
Electronic Systems Quality and Reliability, Enging. Int. 14: 433-447 (1998).
[3] L. Oshiro, R. Radojcic, A Design Methodology for CMOS VLSI Circuits, IRW Final Report 97.
[4] W.H. Gerling, F.W. Wulfert, Qualification for Reliability in Time-to-Market Driven Product Creation
Processes, Int. Rel. Phys. Symp. 2001, Tutorial.
[5] SAE standard J 1879, identical with ZVEI , Handbook for Robustness Validation of Semiconductor
Devices in Automotive Applications, 2007
[6] B. Purvee, R. Susko, J. McCullen, J. Veshinsky, Use Condition Based Reliability Evaluation of New
Package Technologies, , www.sematech.org/public/docubase/abstracts/3813axfr.htm.
[7] P. McClusky, M-Pecht, S. Azarm, J, Pecht, Decreasing Time-to-Market Using Virtual Qualification,
1997 Proc. Inst. of Environmental Sciences.
[8] W. Daukhser, D. Eaton, The Application of Finite Element Modeling to Qualification Testing - A
Knowledge Based Approach, Sematech TCR 99.
[9] R. Blish, N. Durrant, Semiconductor Device Reliability Failure Models, Sematech RTAB, 5/2000,
http://www.sematech.org/public/docubase/abstracts/3813axfr.htm.
[10] JEDEC Publication 122, Failure Mechanisms and Models for Semiconductor Devices.
[11] A. Preussger, N. Lycoudes, R. Blish, S. Huber, T. Dellin, ISMI (Sematech) white paper 04024492A-
TR, “ Understanding and Developing Knowledge-based Qualification of Silicon Devices”, (2004)
[12] H. Keller and A. Preussger, “Robustness Validation”, Tutorial ESREF 2006
