AEC - Q100-007 Rev-B
September 18, 2007
Component Technical Committee
Automotive Electronics Council
ATTACHMENT 7
AEC - Q100-007 Rev-B
FAULT SIMULATION AND FAULT GRADING
AEC - Q100-007 Rev-B
September 18, 2007
Component Technical Committee
Automotive Electronics Council
Acknowledgment
Any document involving a complex technology brings together experience and skills from many sources. The
Automotive Electronics Council would especially like to recognize the following significant contributors to the
development of this document:
Sustaining Members:
Mark A. Kelly Delphi Corporation
Jean Clarac Siemens VDO
Brian Jendro Siemens VDO
Hadi Mehrooz Siemens VDO
Robert V. Knoell Visteon Corporation
Associate Members:
Guest Members:
Tim Haifley Altera David Locker AMRDEC
Daniel Vanderstraeten AMI Semiconductor Jeff Jarvis AMRDEC
Earl Fischer Autoliv
Mike Klucher Cirrus Logic
Xin Miao Zhao Cirrus Logic
Other Contributors:
John Timms Continental Automotive Systems Ramon Aziz Delphi
Roy Ozark Continental Automotive Systems Ken Tumin Freescale
Nick Lycoudes Freescale Matthew Stout Freescale
Kenton Van Klompenberg Gentex Stefan Eichenberger NXP
Werner Kanert Infineon Technologies Amrit Vivekanand Renesas
Elfriede Geyer Infineon Technologies Nicole Cunningham Texas Instruments
John Bertaux International Rectifier Shahin Toutounchi Xilinx
Gary Fisher Johnson Controls
Tom Lawler Lattice Semiconductor
Cliff Jindra Lattice Semiconductor
Scott Daniels Maxim
Tom Tobin Maxim
Mike Buzinski Microchip
Nick Martinez Microchip
Annette Nettles NEC Electronics
Masamichi Murase NEC Electronics
Zhongning Liang NXP Semiconductors
Mark Gabrielle ON Semiconductor
Ken Berry Renesas Technology
Bruce Townsend Spansion
Adam Fogle Spansion
Brian Mielewski STMicroelectronics
James Williams Texas Instruments
Diana Siddall Texas Instruments
Anca Voicu Xilinx
AEC - Q100-007 Rev-B
September 18, 2007
Component Technical Committee
Automotive Electronics Council
NOTICE
AEC documents contain material that has been prepared, reviewed, and approved through the AEC Technical
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AEC documents are designed to serve the automotive electronics industry through eliminating
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assume any obligation whatever to parties adopting the AEC documents. The information included in AEC
documents represents a sound approach to product specification and application, principally from the
automotive electronics system manufacturer viewpoint. No claims to be in conformance with this document
shall be made unless all requirements stated in the document are met.
Inquiries, comments, and suggestions relative to the content of this AEC document should be addressed to
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Published by the Automotive Electronics Council.
This document may be downloaded free of charge, however AEC retains the copyright on this material. By
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Printed in the U.S.A.
All rights reserved
Copyright © 2007 by Delphi, Siemens VDO, and Visteon Corporation. This document may be freely reprinted
with this copyright notice. This document cannot be changed without approval from the AEC Component
Technical Committee.
AEC - Q100-007 Rev-B
September 18, 2007
Component Technical Committee
Automotive Electronics Council
Change Notification
The following summary details the changes incorporated into AEC-Q100-007 Rev-B:
• Section 2, Purpose: Added new statement.
• Section 3, Definitions: Added new definitions section, including items 3.1 to 3.20.
• Figure 1, Typical Fault Simulation and Fault Grading Procedure Flow: Added new Figure
illustrating the typical procedure flow for fault simulation and fault grading.
• Figure 2, Device Simulation: Added new figure illustrating device simulation for integrated
circuits.
• Figures 3 and 4, Fault Types and Fault Models, respectively: Added new figures illustrating
the types of faults and fault models defined in this document.
• Section 4.2.1.1, Stuck-at Fault Model: Added requirements for detection of stuck-at faults.
• Section 4.2.1.3, I
DDQ
Pseudo Stuck-at Fault Model: Added new section; also added sub-
sections 4.2.1.3.1 and 4.2.1.3.2 listing requirements for detection.
• Section 4.2.1.4, Transition Delay Fault Model: Added new section.
• Section 4.2.2, Detectable Fault Simulation for Memory: Added new section; also added sub-
sections 4.2.2.1 to 4.2.2.4.
• Section 4.7 and Figure 6, Types of Stuck-at Faults: Added new section and figure
summarizing the types of stuck-at faults defined in this document.
• Section 4.7.1, Untestable Faults: Provided additional information on untestable faults,
specifically TYPE1 and TYPE2 faults.
• Section 4.7.1.1, TYPE1 Untestable Faults: Added wording, and added sections where
applicable, to define the primary categories of TYPE1 untestable faults.
• Section 4.7.1.2, TYPE2 Untestable Faults: Added wording, and new sections where
applicable, to define the primary categories of TYPE2 untestable faults.
• Section 4.7.2, Testable Faults: Added wording, and new sections where applicable, to
define the primary categories of faults detected by implication.
• Section 5.3, Test Coverage: Modified equation used to calculate percent of faults detected
to improve clarity. Added wording, and new sections where applicable, to better define the
various aspects of test, test coverage, and coverage reporting.
• Section 6, Acceptance Criteria: Added wording, and new sections where applicable, to
better define the qualification requirements (both analog and digital circuits), theoretical
field reject rate, test sequence alterations ,and production fault coverage.
AEC - Q100-007 Rev-B
September 18, 2007
Component Technical Committee
Automotive Electronics Council
Page 1 of 21
METHOD - 007
FAULT SIMULATION AND FAULT GRADING
Text enhancements and differences made since the last revision of this
document are shown as underlined areas.
1. SCOPE
This test method defines fault grading procedure and specifies a level to which the manufacturing test
program for the device under test must detect faults. Parametric failures are not covered. Another
term for fault grading is fault simulation. Fault grading applies to all digital circuits including the digital
portion of mixed signal and linear circuits. Fault grading does not apply to the linear portion of the
circuits.
Also, this document covers modeling and logic simulation requirements; the assumed fault model and
fault simulation requirements; and the procedure that must be followed to evaluate and report test
coverage.
2. PURPOSE
Device quality is determined by three factors:
• Quality of the fault model: Does the fault model adequately model the effect of
manufacturing defects?
• Fault coverage: Given a fault model, how many or the circuit primitives are tested
against these faults?
• Environmental defect activation conditions: Some defects manifest themselves only
(or more prominently) at certain activation conditions (voltage, temperature,
frequency). These activation conditions hence need be reflected in the test setup to
be effective.
The purpose of this test method is to develop the optimal fault coverage of the component using
current fault simulation models in order to minimize defects and report the fault coverage metric to the
end user.
This test method does not discuss the validity of the fault models nor the proper activation conditions.
3. DEFINITIONS
3.1 Blocked Fault
A single stuck-at fault for which no test exists because the propagation path (to an observed node) is
blocked.
3.2 Collapsed Fault
One single stuck-at fault for each fault equivalence grouping. The representative fault is the one at
the location furthest downstream in the cells for the faults in the equivalence grouping.
