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### ADI RFIC ADRV9009 数据手册解析 #### 概述 ADI RFIC ADRV9009 是一款高度集成的射频 (RF) 敏捷收发器，提供双发射器、接收器以及集成的合成器功能，并支持数字信号处理。这款芯片在3G、4G及5G宏基站时分双工 (TDD) 应用场景中，以其卓越的性能和低功耗特性脱颖而出。 #### 特点详解 ##### 双发射器与接收器 - **双发射器**: 支持两个独立的发射通道，能够同时发射不同的信号。 - **双接收器**: 包含两个独立的接收通道，每个通道都具备先进的动态范围，适用于多种通信场景。 - **观察接收器**: 设备还包含一个共享的时间共享观察接收器 (ORx)，用于监测发射信号和环境信号，在 TDD 场景中特别有用。 ##### 高性能与宽带宽 - **最大接收带宽**: 达到200MHz，能够支持高速数据传输。 - **可调谐发射合成器的最大带宽**: 为450MHz，提供了更宽广的频率选择范围。 - **观察接收器最大带宽**: 同样达到450MHz，确保了对复杂信号的有效分析。 ##### 高度集成化 - **全集成分数N型射频合成器**: 提供稳定的频率输出，减少外部组件需求。 - **全集成时钟合成器**: 为系统提供精准的时钟信号，简化设计复杂度。 - **多芯片相位同步**: 实现射频本地振荡器 (RF LO) 和基带时钟之间的精确同步，提升整体系统的稳定性和可靠性。 ##### 接口与标准 - **JESD204B 数据路径接口**: 支持高速数据传输，兼容最新的通信标准，降低了数据延迟并提高了传输效率。 ##### 调谐范围 - **中心频率调谐范围**: 从75MHz至6000MHz，覆盖了广泛的应用领域。 #### 应用场景 - **3G、4G及5G TDD 宏基站**: 适用于新一代无线通信网络中的核心设备。 - **TDD 主动天线系统**: 在主动天线系统中实现高精度的时间同步。 - **大规模多输入多输出 (MIMO)**: 通过多个天线实现更高数据传输速率和更强抗干扰能力。 - **相控阵雷达**: 在军事和民用雷达系统中发挥重要作用。 - **电子战**: 用于对抗和侦察等高级别通信对抗领域。 - **军用通信**: 在复杂电磁环境中确保安全可靠的通信链路。 - **便携式测试设备**: 适用于实验室和现场测试环境。 #### 一般描述 - **集成化优势**: ADRV9009 的高度集成减少了外围组件的数量，简化了电路板布局。 - **高性能与低功耗**: 在保证高性能的同时，降低了功耗，适合于需要高效能比的场合。 - **接收路径**: 包括两个独立的宽带直接转换接收器，具有业界领先的动态范围。 - **观察路径接收器**: 该接收器支持时间共享模式，可在 TDD 场景中监测发射信号和周围环境信号。 - **完整的接收子系统**: 内置自动和手动衰减控制、直流偏移校正、正交误差校正 (QEC) 和数字滤波等功能，大大减少了额外硬件的需求。 #### 总结 ADI RFIC ADRV9009 数据手册提供了关于这款高性能收发器的全面信息，包括其特点、技术规格和应用场景。对于从事5G技术开发的专业人士而言，深入理解这些细节将有助于更好地利用这款芯片的优势，推动通信技术的进步。

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Integrated Dual RF Transmitter, Receiver,

and Observation Receiver

Data Sheet

ADRV9009

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

Dual transmitters

Dual receivers

Dual input shared observation receiver

Maximum receiver bandwidth: 200 MHz

Maximum tunable transmitter synthesis bandwidth:

450 MHz

Maximum observation receiver bandwidth: 450 MHz

Fully integrated fractional-N RF synthesizers

Fully integrated clock synthesizer

Multichip phase synchronization for RF LO and baseband

clocks

JESD204B datapath interface

Tuning range (center frequency): 75 MHz to 6000 MHz

APPLICATIONS

3G, 4G, and 5G TDD macrocell base stations

TDD active antenna systems

Massive multiple input, multiple output (MIMO)

Phased array radar

Electronic warfare

Military communications

Portable test equipment

GENERAL DESCRIPTION

The ADRV9009 is a highly integrated, radio frequency (RF), agile

transceiver offering dual transmitters and receivers, integrated

synthesizers, and digital signal processing functions. The IC

delivers a versatile combination of high performance and low

power consumption demanded by 3G, 4G, and 5G macro cell

time division duplex (TDD) base station applications.

The receive path consists of two independent, wide bandwidth,

direct conversion receivers with state-of-the-art dynamic range.

The device also supports a wide bandwidth, time shared

observation path receiver (ORx) for use in TDD applications.

The complete receive subsystem includes automatic and

manual attenuation control, dc offset correction, quadrature error

correction (QEC), and digital filtering, thus eliminating the need

for these functions in the digital baseband. Several auxiliary

functions, such as analog-to-digital converters (ADCs), digital-to-

analog converters (DACs), and general-purpose inputs/outputs

(GPIOs) for the power amplifier (PA), and RF front-end

control are also integrated.

In addition to automatic gain control (AGC), the ADRV9009

also features flexible external gain control modes, allowing

significant flexibility in setting system level gain dynamically.

The received signals are digitized with a set of four high dynamic

range, continuous time Σ-Δ ADCs that provide inherent

antialiasing. The combination of the direct conversion

architecture, which does not suffer from out of band image

mixing, and the lack of aliasing, relaxes the requirements of the

RF filters when compared to traditional intermediate frequency

(IF) receivers.

The transmitters use an innovative direct conversion

modulator that achieves high modulation accuracy with

exceptionally low noise.

The observation receiver path consists of a wide bandwidth,

direct conversion receiver with state-of-the-art dynamic range.

The fully integrated phase-locked loop (PLL) provides high

performance, low power, fractional-N RF frequency synthesis

for the transmitter (Tx) and receiver (Rx) signal paths. An

additional synthesizer generates the clocks needed for the

converters, digital circuits, and the serial interface. A multichip

synchronization mechanism synchronizes the phase of the RF

local oscillator (LO) and baseband clocks between multiple

ADRV9009 chips. Precautions are taken to provide the isolation

required in high performance base station applications. All

voltage controlled oscillators (VCOs) and loop filter

components are integrated.

The high speed JESD204B interface supports up to 12.288 Gbps

lane rates, resulting in two lanes per transmitter and a single

lane per receiver in the widest bandwidth mode. The interface

also supports interleaved mode for lower bandwidths, thus

reducing the total number of high speed data interface lanes to

one. Both fixed and floating point data formats are supported.

The floating point format allows internal AGC to be invisible to

the demodulator device.

The core of the ADRV9009 can be powered directly from 1.3 V

regulators and 1.8 V regulators, and is controlled via a standard

4-wire serial port. Comprehensive power-down modes are

included to minimize power consumption in normal use. The

ADRV9009 is packaged in a 12 mm × 12 mm, 196-ball chip

scale ball grid array (CSP_BGA).

ADRV9009 Data Sheet

Rev. B | Page 2 of 127

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 4

Specifications ..................................................................................... 5 

Current and Power Consumption Specifications ................... 14

Timing Diagrams ........................................................................ 15

Absolute Maximum Ratings .......................................................... 16

Reflow Profile .............................................................................. 16

Thermal Management ............................................................... 16

Thermal Resistance .................................................................... 16

ESD Caution ................................................................................ 16

Pin Configuration and Function Descriptions ........................... 17

Typical Performance Characteristics ........................................... 23

75 MHz to 525 MHz Band ........................................................ 23

650 MHz to 3000 MHz Band .................................................... 44

3400 MHz to 4800 MHz Band .................................................. 63

5100 MHz to 5900 MHz Band .................................................. 80

Transmitter Output Impedance ................................................ 95

Observation Receiver Input Impedance .................................. 95

Receiver Input Impedance......................................................... 96

Terminology .................................................................................... 97

Theory of Operation ...................................................................... 98

Transmitter .................................................................................. 98

Receiver........................................................................................ 98

Observation Receiver ................................................................. 98

Clock Input .................................................................................. 98

Synthesizers ................................................................................. 98

SPI ................................................................................................. 99

JTAG Boundary Scan ................................................................. 99

Power Supply Sequence ............................................................. 99

GPIO_x Pins ............................................................................... 99

Auxiliary Converters .................................................................. 99

JESD204B Data Interface .......................................................... 99

Applications Information ............................................................ 101

PCB Layout and Power Supply Recommendations ............. 101

PCB Material and Stackup Selection ..................................... 101

Fanout and Trace Space Guidelines ....................................... 103

Component Placement and Routing Guidelines ................. 104

RF and JESD204B Transmission Line Layout ...................... 110

Isolation Techniques Used on the ADRV9009-W/PCBZ ... 114

RF Port Interface Information ................................................ 116

Outline Dimensions ..................................................................... 127

Ordering Guide ........................................................................ 127

REVISION HISTORY

5/2019—Rev. A to Rev B.

Replaced ADRV9009 Customer Card to

ADRV9009-WPCBZ ..................................................... Throughout

Changes to Features Section............................................................ 1

Changes to Figure 1 .......................................................................... 4

Changes to Specifications Section and Table 1 ............................. 5

Change to Figure 2 ......................................................................... 15

Changes to Table 3 and Thermal Resistance Section ................. 16

Changes to 75 MHz to 525 MHz Band Section, Figures and

Captions ........................................................................................... 23

Deleted Figure 83 to Figure 85; Renumbered Sequentially ...... 34

Added Figure 78, Figure 79, and Figure 80; Renumbered

Sequentially ..................................................................................... 35

Added Figure 90 .............................................................................. 37

Added Figure 125 to Figure 127 ................................................... 43

Changes to 650 MHz to 3000 MHz Band Section, Figures and

Captions ........................................................................................... 44

Changes to 3400 MHz to 4800 MHz Band Section, Figures and

Captions ........................................................................................... 63

Changes to 5100 MHz to 5900 MHz Band Section, Figures and

Captions ........................................................................................... 80

Changes to Terminology Section ................................................. 97

Deleted Figure 432 ......................................................................... 98

Changes to Theory of Operation Section and Clock

Input Section ................................................................................... 98

Changed Serial Peripheral Interface Section to SPI Section and

AUX DAC_x Section to Auxiliary DAC x Section ......................... 99

Changes to Power Supply Sequence Section, GPIO_x Pins

Section, Auxiliary DAC x Section, and JESD204B Data

Interface Section ............................................................................. 99

Changes to Table 7 Title, Figure 430, and Figure 431................... 100

Changes to Overview Section, PCB Material and Stackup

Selection Section, and Figure 432 Caption ............................... 101

Changes to Table 9 and Table 10 ................................................ 102

Changes to Fanout and Trace Space Guidelines Section ......... 103

Changes to Signals with Highest Routing Priority Section and

Figure 434 ...................................................................................... 104

Change to Figure 435 Caption .................................................... 105

Changes to Signals with Second Routing Priority Section and

Figure 436 ...................................................................................... 106

Changes to Figure 437 ................................................................. 107

Changes to Figure 438 ................................................................. 108

Data Sheet ADRV9009

Rev. B | Page 5 of 127

SPECIFICATIONS

Electrical characteristics at VDDA1P3

= 1.3 V, VDDD1P3_DIG = 1.3 V, VDDA1P8_TX = 1.8 V, junction temperature (T

) = full

operating temperature range. LO frequency (f

) = 1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer

to the Typical Performance Characteristics section for input and output circuit path loss. The device configuration profile for the 75 MHz to

525 MHz frequency range is as follows: receiver = 50 MHz bandwidth (inphase quadrature (IQ) rate = 61.44 MHz), transmitter = 50 MHz

transmitter large signal bandwidth and 100 MHz transmitter synthesis bandwidth (IQ rate = 122.88 MHz), observation receiver = 100 MHz

bandwidth (IQ rate = 122.88 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz. Unless otherwise specified, the device

configuration for all other frequency ranges is as follows: receiver = 200 MHz bandwidth (IQ rate = 245.76 MHz), transmitter = 200 MHz

transmitter large signal bandwidth and 450 MHz transmitter synthesis bandwidth (IQ rate = 491.52 MHz), observation receiver = 450 MHz

bandwidth (IQ rate = 491.52 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

TRANSMITTERS

Center Frequency 75 6000 MHz

Transmitter Synthesis

Bandwidth

450 MHz

Transmitter Large Signal

Bandwidth

200 MHz

Peak-to-Peak Gain

Deviation

1.0 dB

450 MHz bandwidth, compensated by

programmable finite impulse response

(FIR) filter

Gain Slope ±0.1 dB

Any 20 MHz bandwidth span,

compensated by programmable FIR

filter

Deviation from Linear Phase 1 Degrees 450 MHz bandwidth

Transmitter Attenuation

Power Control Range

0 32 dB

Signal-to-noise ratio (SNR) maintained

for attenuation between 0 dB and 20 dB

Transmitter Attenuation

Power Control Resolution

0.05 dB

Transmitter Attenuation

Integral Nonlinearity

INL 0.1 dB For any 4 dB step

Transmitter Attenuation

Differential Nonlinearity

DNL 0.04 dB Monotonic

Transmitter Attenuation

Serial Peripheral

Interface 2 (SPI 2) Timing

See Figure 4

Time from CS Going High

to Change in Transmitter

Attenuation

SCH

19.5 24 ns

Time Between Consecutive

Microattenuation Steps

ACH

6.5 8.1 ns

A large change in attenuation can be

broken up into a series of smaller

attenuation changes

Time Required to Reach

Final Attenuation Value

DCH

800 ns

Time required to complete the change

in attenuation from start attenuation

to final attenuation value

Maximum Attenuation

Overshoot During

Transition

−1.0 +0.5 dB

Change in Attenuation per

Microstep

0.5 dB

Maximum Attenuation

Change when CS

Goes

High

32 dB

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