1 2 3 4 56
A
B
C
D
6
54321
D
C
B
A
Title
Number RevisionSize
B
Date: 23-Apr-2005 Sheet of
File: F:\
我的文件\毕业设计\华华\毕业设计电路图纸.ddbDrawn By:
12
34
56
78
910
J1
JTAG
TDO
1
DCLK
4
TCK
3
DATA
2
VCCSEL
5
NC
6
NC
7
OE
8
nCS
9
GND
10
TDI
11
nCASC
12
nINIT_CONF
13
VPPSEL
14
NC
15
NC
16
NC
17
VPP
18
TMS
19
VCC
20
U2
EPC2
R1
10K
R2
10K
R3
10K
R4
1K
R5
1K
R6
1K
R7
1K
R8
1K
R9
1K
TDO
E_TDO
F_TDO
1
2
3
J2
TDO
E_TDO
F_TDO
VCC
VCC
TCK
77
TDO
74
TMS
57
TDI
15
DATA
12
DCLK
13
nSTATUS
55
CONF_DONE
76
nCONFIG
34
nCE
14
MSEL0
31
MSEL1
32
nCEO
75
GND
2
GND
9
GND
16
GND
22
GND
46
GND
44
GND
43
GND
42
GND
41
GND
35
VCC
63
VCC
45
VCC
40
VCC
33
VCC
20
VCC
4
GND
84
GND
83
GND
30
GND
29
GND
82
GND
28
GND
26
GND
81
GND
80
GND
79
GND
78
GND
73
GND
72
GND
71
GND
70
GND
69
GND
68
GND
67
GND
54
GND
53
GND
52
GND
47
D0
58
D1
59
D2
60
D3
61
D4
62
D5
64
D6
65
D7
66
CLK
1
clrn
3
k
10
EPF10K10LC
g
11
a3
48
a2
49
a1
50
a0
51
b3
36
b2
37
b1
38
b0
39
c3
23
c2
24
c1
25
c0
27
d3
17
d2
18
d1
19
d0
21
e3
8
e2
7
e1
6
e0
5
TRST
56
U1 EPF10K
VCC
拨码开关组
a1
3
a2
5
a3
7
b0
9
a0
1
b1
11
b2
13
b3
15
c0
17
c1
19
c2
21
c3
23
d0
25
d1
27
d2
29
d3
31
e0
33
e1
35
e2
37
e3
39
GND
2
J3
BOPAN
VCC
GND
CLK
NC
XTAL
32.768MHz
CLK
CLK
VCC
C1
0.1u
VCC
+5V
C2
0.1u
1
2
3
6
5
4
BOPAN
CLRN
G
K
VCC
CLRN
K
G
VCC
D0
7
CS
1
WR1
2
AGND
3
D3
4
D2
5
D1
6
Vref
8
Rfb
9
DGND
10
Iout2
11
Iout1
12
D7
13
D6
14
D5
15
D4
16
XFER
17
WR2
18
ILE
19
Vcc
20
DAC0832
U3
DAC0832
VCC
D1 D2
2
3
6
5
4
71
U4
uA741
RW
15K
+5V
VCC
+12V
D0
D1
D2
D3
D4
D5
D6
D7
LPF
a3
a2
a1
a0
b3
b2
b1
b0
c3
c2
c1
c0
d3
d2
d1
d0
e3
e2
e1
e0
D0
D1
D2
D3
D4
D5
D6
D7
a3
a2
a1
a0
b3
b2
b1
b0
c3
c2
c1
c0
d3
d2
d1
d0
e3
e2
e1
e0
+5V
+5V
+5V
+5V
+5V
+5V
+5V
VCC
-12V
R10
470
R11
1.5k
R12
4k
C3
0.1u
GND
OUT
IN
7805
C4
0.33u
+12V VCC+12v
-12v
+5V
R13
2k
R14
2k
R15
2k
R16
2k
C8
100pf
C9
0.1u
C7
100PF
C6
100pf
C5
100pf
OUT
LPF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RP1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RP3
VCC
+5V
c0
c1
c2
c3
b3
b2
b1
b0
a3
a2
a1
a0
d0
d1
d2
d3
e0
e1
e2
e3
1
2
3
4
8
7
6
5
RP2
Designed by POPLAR
2005.4.20
