JEDEC Standard No. 21-C [SPD]
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Release 25
JEDEC Standard No. 21-C
Page 4.1.2.M-1 – 1
JESD 21-C Section Title: Annex M: Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules
Committee Document Reference Title: LPDDR3 and LPDDR4 SPD Document Release 1
Device Type Identifier: LP-DIMM Revision 1.0
1 Scope
This Annex describes the serial presence detect (SPD) values for all LPDDR modules. Differences between module types are
encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for
‘Specific Features’. The following SPD fields will be documented in the order presented in Section 2, with the exception of bytes
128~255 which are documented in separate sections, one for each family of module types. Further description of Byte 2 is found in
Annex A of the SPD standard.
All unused entries will be coded as 0x00. All unused bits in defined bytes will be coded as 0 except where noted.
Timing parameters in the SPD represent the operation of the module including all Drams and support devices at the lowest supported
supply voltage (see SPD byte 11), and are valid from t
CKAVG
min to t
CKAVG
max (see SPD bytes 18 and 19).
To allow for maximum flexibility as devices evolve, SPD fields described in this document may support device configuration and
timing options that are not included in the JEDEC LPDDR SDRAM data sheet (JESD79-4). Please refer to DRAM supplier data
sheets or JESD79-4 to determine the compatibility of components.
2 Address map
The following is the SPD address map for all LPDDR modules. It describes where the individual lookup table entries will be held in
the serial EEPROM. Consistent with the definition of LPDDR generation SPD devices which have four individual write protection
blocks of 128 bytes in length each, the SPD contents are aligned with these blocks as shown in Table 1.
2.1 Block Descriptions
2.1.1 Block 0: Base Configuration and DRAM Parameters
Table 2 details the location of each byte in this block.
Table 1 — Address Map
Block Range Description
0 0~127 0x000~0x07F Base Configuration and DRAM Parameters
1 128~255 0x080~0x0FF Module Specific Parameters -- See annexes for details
2
256~319 0x100~0x13F
Hybrid Memory Parameters
320~383 0x140~0x17F Manufacturing Information
3 384~511 0x180~0x1FF End User Programmable
Table 2 — Block 0: Base Configuration and DRAM Parameters
Byte Number
Function Described
Notes
0 0x000 Number of Serial PD Bytes Written / SPD Device Size 1, 2
1 0x001 SPD Revision
2 0x002 Key Byte / DRAM Device Type
3 0x003 Key Byte / Module Type
4 0x004 SDRAM Density and Banks 3
5 0x005 SDRAM Addressing 3
NOTE 1 Number of SPD bytes written will typically be programmed as 384 bytes.
NOTE 2 Size of SPD device will typically be programmed as 512 bytes.
NOTE 3 From LPDDR SDRAM data sheet.
NOTE 4 These are optional, in accordance with the JEDEC specification.
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