华邦w25x16 SPIFlash Read ID FPGA(EP4CE6)实验Verilog逻辑源码Quartus工程文件+文...

华邦w25x16 SPIFlash Read ID FPGA(EP4CE6)实验Verilog逻辑源码Quartus工程文件+文档说明资料，FPGA为CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件，可以做为你的学习设计参考。 **------------------------------------------------------------------------------------------------------ ** Modified by: ** Modified date: ** Version: ** Descriptions: Read the Device ID of the W25X16 Flash ** **------------------------------------------------------------------------------------------------------ ********************************************************************************************************/ module W25X16 ( //input signal input sys_clk , input sys_rst_n , input W25X16_DO , //output signal output reg W25X16_CS , output reg W25X16_CLK , output reg W25X16_DIO , output reg [7:0] LED ); //reg define reg [5:0] counter ; reg [5:0] clk_cnt ; reg [15:0] shift_buf ; //wire define wire div_clk1 ; wire div_clk2 ; /******************************************************************************************************* ** Main Program ** ********************************************************************************************************/ //creat a clock about 1MHz always @(posedge sys_clk or negedge sys_rst_n) begin if ( sys_rst_n ==1'b0 ) clk_cnt <= 6'b0; else clk_cnt <= clk_cnt + 1'b1; end assign div_clk1 = clk_cnt[5]; assign div_clk2 = ~clk_cnt[5]; //get a counter that width is 6 bits always @(posedge div_clk1 or negedge sys_rst_n) begin if ( sys_rst_n ==1'b0 ) counter <= 6'b0; else counter <= counter + 6'b1; end //get the enable signal of the w25x16,and the low level effectively always @(*) begin if ( counter >= 8 && counter <= 58 ) W25X16_CS <= 1'b0;