Xilinx SPARTAN6 XC6SLX9 FPGA SDRAM测试 ISE工程Verilog源码+硬件PDF原理图

基于Xilinx FPGA SPARTAN6 XC6SLX9 FPGA SDRAM测试 ISE工程Verilog源码+硬件PDF原理图 module top_tb; // Inputs reg mclk; reg system_rst; // Outputs wire good; wire error; wire [1:0] dqm; wire [12:0] sa; wire [1:0] ba; wire sdclk; wire cke; wire cs_n; wire ras_n; wire cas_n; wire we_n; wire [7:0] Port1; wire [7:0] Port2; wire [7:0] Port3; wire [7:0] Port4; wire [7:0] Port5; wire [7:0] Port6; // Bidirs wire [15:0] dq; // Instantiate the Unit Under Test (UUT) sdram_drive uut ( .mclk(mc