1
DDR System Design
Considerations
Integrated Technology Group
Micron
2
DDR Overview
December, 00 3
SSTL2 Signal Levels
Driver
Receiver
December, 00 4
SSTL2 Double Ended Termination
VTT Termination Island
Address / Command
VTT/VREF
Generator
Data/Strobe/Mask
Chip Selects
SSTL_2
SSTL_2
PC266
SDRAM
Reg.
DIMM
PC266
SDRAM
Reg.
DIMM
VTTTermination Island
Address/Cmnd
Chipset
“North
Bridge”
December, 00 5
SSTL2 Single Ended Termination
VTT Termination Island
Address/Command
VTT/VREF
Generator
Data/Strobe/Mask
Chip Selects
SSTL_2
SSTL_2
PC266
SDRAM
Reg.
DIMM
PC266
SDRAM
Reg.
DIMM
Address/Cmnd
Chipset
“North
Bridge”
