MAX 10 FPGA Device Architecture.pdf

MAX 10 FPGA Device Architecture

2014.12.15

M10-ARCHITECTURE

Subscribe

Send Feedback

The MAX

®

10 devices consist of the following:

• Logic array blocks (LABs)

• Analog-to-digital converter (ADC)

• External memory interfaces

• Configuration flash memory (CFM)

©

trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance

of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

• The amount and location of each block varies in each MAX 10 device.

• Certain MAX 10 devices may not contain a specific block.

• MAX 10 Device Datasheet

• MAX 10 FPGA Device Overview

The LABs are configurable logic blocks that consist of a group of logic resources.

Each LAB consists of the following:

• 16 logic elements (LEs)—smallest logic unit in MAX 10 devices

MAX 10 FPGA Device Architecture

Send Feedback

The direct link connection minimizes the use of row and column interconnects to provide higher

performance and flexibility. The direct link connection enables the neighboring elements from left and

right to drive the local interconnect of a LAB. The elements are:

• LABs

• PLLs

• M9K embedded memory blocks

• embedded multipliers

Each LE can drive up to 48 LEs through local and direct link interconnects.

• Two clock enable signals

• Two asynchronous clear signals

• One synchronous clear signal

• One synchronous load signal

MAX 10 FPGA Device Architecture

Send Feedback

• Each LAB can use two clocks signals. The clock and clock enable signals