Document
Number
Revision
Number
Description Date
,AEP
and DDR4
/AEP 2LM
Socket Level Population Requirements;
removed in the General Population Requirements Section the
statement of " Mixing of NVDIMMs and AEP DIMMs within the
same channel or within iMC is not allowed", since NVDIMM is
not Purley POR;
Updated via count for all signal group to consider SMT
connector coverage; included VPP referencing as far
referencing on all DDR tables to clarify options as noted at the
beginning of the chapter; updated bottom layer DQ length to
2700 mils.
• Chapter 8: added note for SSD topologies loss requirement;
removed SSD CEM note in section 8.5.8; added cable
requirement section; updated PCIe SSD and standard topology
lengths and via stub requirements
• Chapter 10: Updated EndPoint Only (EPO) PCH Signal
Connectivity Requirements
• Chapter 11: added note for SSD topologies loss requirement;
removed SSD CEM note in section 8.5.8; added cable
requirement section
• Chapter 13: corrected SPI flash size requirements for ME
support
• Chapter 14: minor updates to JTAG and MBP guidelines for 8-
socket configuration
• Chapter 15: Updated Pmax.app numbers for both 165w and
145w in Table 209; Updated VDDQ total allowable tolerance at
CPU VCCD cavity caps and Max load step @ CPU side for select
SKUs on Purley refresh in Table 228; Updated VPP Max step
load and slew rate @ CPU side for select SKUs on Purley
refresh in Table 233; Updated max load TDC/Iccmax current,
max step load size for some Lewisburg SKUs in Table 244;
Conductivity Equation added to General Motherboard
guidelines section 15.3.1.8; Updated the Auto Detect PMax
correction Factor section 15.3.16
• Chapter 16: updated NCSI routing guidelines
• Chapter 17: Updated reset timing diagrams for power up and
power down reset sequences.
•
546835
0.97 • Chapter 3: clarified intra-pair length matching guideline;
adjusted several rules for 10GbE including Serpentine routing
rule, Routing over split power plane, Trace corner guideline,
via placement, Microstrip via routing, DC blocking cap pad
ground voiding and broadside coupled stripline guideline;
clarified PCIe lane reversal guideline
• Chapter 4: clarification on how SRC, PLAT and ITPXDP clocks
can be used; minor updates to the Integrated Ethernet
Controller 25MHz Crystal Layout guidelines
• Chapter 5: updated routing guideline tables for each topology;
added Trade Off table for topology 6
• Chapter 7: Made correction to the LFend and LFinner values for
break-out and open field region for Figure 188 (DDR4/DDR-T
Source-Synchronous Signal Group Routing Guidelines,
DQ[63:00], DQS_{DP/DN}[17:00], ECC[7:0], 2SPC;Up to 93
mils Stackup, Part4 - Optional Interdigital Tab)
• Chapter 8: added note about lane reversal implementation;
added AC cap values for DMI3
• Chapter 10: clarification on EPO PCH WoL (Wake-On-Line)
power sequencing considerations
December 2015
continued...
Purley—Revision History
Purley
Platform Design Guide October 2016
4 Intel Confidential Doc. No.: 546835, Rev.: 1.6
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