HEADER:0000000100000000 ;
HEADER:0000000100000000 ; +-------------------------------------------------------------------------+
HEADER:0000000100000000 ; | This file was generated by The Interactive Disassembler (IDA) |
HEADER:0000000100000000 ; | Copyright (c) 2022 Hex-Rays, <support@hex-rays.com> |
HEADER:0000000100000000 ; +-------------------------------------------------------------------------+
HEADER:0000000100000000 ;
HEADER:0000000100000000 ; Input SHA256 : 0D2B2F0E5D3BF95B7FDCC3BD465B0D34C9597AF3DDE635839866483EEFE43F9B
HEADER:0000000100000000 ; Input MD5 : 4A2234EBDE251890B142C57DA8754FA5
HEADER:0000000100000000 ; Input CRC32 : 1B042DAF
HEADER:0000000100000000
HEADER:0000000100000000
HEADER:0000000100000000 ; Processor : ARM
HEADER:0000000100000000 ; ARM architecture: metaarm
HEADER:0000000100000000 ; Target assembler: Generic assembler for ARM
HEADER:0000000100000000 ; Byte sex : Little endian
HEADER:0000000100000000
HEADER:0000000100000000 ; ===========================================================================
HEADER:0000000100000000
HEADER:0000000100000000 ; [00003BBC BYTES: COLLAPSED SEGMENT HEADER. PRESS CTRL-NUMPAD+ TO EXPAND]
__text:0000000100003BBC ; ===========================================================================
__text:0000000100003BBC
__text:0000000100003BBC ; Segment type: Pure code
__text:0000000100003BBC AREA __text, CODE
__text:0000000100003BBC ; ORG 0x100003BBC
__text:0000000100003BBC CODE64
__text:0000000100003BBC
__text:0000000100003BBC ; =============== S U B R O U T I N E =======================================
__text:0000000100003BBC
__text:0000000100003BBC ; Attributes: bp-based frame
__text:0000000100003BBC
__text:0000000100003BBC ; int __cdecl main(int argc, const char **argv, const char **envp)
__text:0000000100003BBC EXPORT _main
__text:0000000100003BBC _main
__text:0000000100003BBC
__text:0000000100003BBC anonymous_0= -0x108
__text:0000000100003BBC var_100= -0x100
__text:0000000100003BBC var_F8= -0xF8
__text:0000000100003BBC var_F4= -0xF4
__text:0000000100003BBC var_F0= -0xF0
__text:0000000100003BBC var_EC= -0xEC
__text:0000000100003BBC var_E8= -0xE8
__text:0000000100003BBC var_E4= -0xE4
__text:0000000100003BBC var_E0= -0xE0
__text:0000000100003BBC var_DC= -0xDC
__text:0000000100003BBC var_D8= -0xD8
__text:0000000100003BBC var_D0= -0xD0
__text:0000000100003BBC var_C4= -0xC4
__text:0000000100003BBC var_C0= -0xC0
__text:0000000100003BBC var_B4= -0xB4
__text:0000000100003BBC __dst= -0xB0
__text:0000000100003BBC var_18= -0x18
__text:0000000100003BBC var_10= -0x10
__text:0000000100003BBC var_8= -8
__text:0000000100003BBC var_s0= 0
__text:0000000100003BBC
__text:0000000100003BBC FC 6F BE A9 STP X28, X27, [SP,#-0x10+var_10]!
__text:0000000100003BC0 FD 7B 01 A9 STP X29, X30, [SP,#0x10+var_s0]
__text:0000000100003BC4 FD 43 00 91 ADD X29, SP, #0x10
__text:0000000100003BC8 FF 03 04 D1 SUB SP, SP, #0x100
__text:0000000100003BCC 08 00 00 B0 ADRP X8, #___stack_chk_guard_ptr@PAGE
__text:0000000100003BD0 08 09 40 F9 LDR X8, [X8,#___stack_chk_guard_ptr@PAGEOFF]
__text:0000000100003BD4 08 01 40 F9 LDR X8, [X8]
__text:0000000100003BD8 A8 83 1E F8 STUR X8, [X29,#var_18]
__text:0000000100003BDC BF C3 14 B8 STUR WZR, [X29,#var_B4]
__text:0000000100003BE0 08 00 00 90 08 11 3A 91 ADRL X8, aFlagXxxxxxxxxx ; "flag{xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx}"
__text:0000000100003BE8 A8 03 14 F8 STUR X8, [X29,#var_C0]
__text:0000000100003BEC A0 C3 02 D1 SUB X0, X29, #-__dst ; __dst
__text:0000000100003BF0 01 00 00 90 21 40 3C 91 ADRL X1, unk_100003F10 ; __src
__text:0000000100003BF8 02 13 80 D2 MOV X2, #0x98 ; __n
__text:0000000100003BFC 99 00 00 94 BL _memcpy
__text:0000000100003BFC
__text:0000000100003C00 A0 03 54 F8 LDUR X0, [X29,#var_C0] ; __s
__text:0000000100003C04 9D 00 00 94 BL _strlen
__text:0000000100003C04
__text:0000000100003C08 E8 03 00 AA MOV X8, X0
__text:0000000100003C0C A8 C3 13 B8 STUR W8, [X29,#var_C4]
__text:0000000100003C10 A8 C3 53 B8 LDUR W8, [X29,#var_C4]
__text:0000000100003C14 08 05 00 11 ADD W8, W8, #1
__text:0000000100003C18 E9 03 00 91 MOV X9, SP
__text:0000000100003C1C A9 03 13 F8 STUR X9, [X29,#var_D0]
__text:0000000100003C20 09 F5 7E D3 LSL X9, X8, #2
__text:0000000100003C24 29 3D 00 91 ADD X9, X9, #0xF
__text:0000000100003C28 29 ED 7C 92 AND X9, X9, #0xFFFFFFFFFFFFFFF0
__text:0000000100003C2C AA 23 00 D1 SUB X10, X29, #-var_8
__text:0000000100003C30 49 01 10 F8 STUR X9, [X10,#-0x100]
__text:0000000100003C34 10 00 00 B0 ADRP X16, #___chkstk_darwin_ptr@PAGE
__text:0000000100003C38 10 02 40 F9 LDR X16, [X16,#___chkstk_darwin_ptr@PAGEOFF]
__text:0000000100003C3C 00 02 3F D6 BLR X16
__text:0000000100003C3C
__text:0000000100003C40 A9 23 00 D1 SUB X9, X29, #-var_8
__text:0000000100003C44 2A 01 50 F8 LDUR X10, [X9,#-0x100]
__text:0000000100003C48 E9 03 00 91 MOV X9, SP
__text:0000000100003C4C 29 01 0A EB SUBS X9, X9, X10
__text:0000000100003C50 3F 01 00 91 MOV SP, X9
__text:0000000100003C54 A9 03 10 F8 STUR X9, [X29,#var_100]
__text:0000000100003C58 A8 83 12 F8 STUR X8, [X29,#var_D8]
__text:0000000100003C5C BF 43 12 B8 STUR WZR, [X29,#var_DC]
__text:0000000100003C60 01 00 00 14 B loc_100003C64
__text:0000000100003C60
__text:0000000100003C64 ; ---------------------------------------------------------------------------
__text:0000000100003C64
__text:0000000100003C64 loc_100003C64
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