【免费】数字ic设计面试基础知识_ic设计面试资源-CSDN文库

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第一章数字芯片流程 ......................................................................................................................5

第二章数字电路基础 ......................................................................................................................6

2.1 逻辑函数化简 ......................................................................................................................6

2.2 竞争冒险 ............................................................................................................................7

2.3 组合逻辑设计 ......................................................................................................................8

2.3.1 译码器........................................................................................................................8

2.3.2 奇偶校验电路............................................................................................................9

2.3.3 数据比较器..............................................................................................................10

2.3.4 全加器、半加器、超前进位加法器......................................................................10

2.4 CMOS 门电路....................................................................................................................11

2.5 反相器知识 ........................................................................................................................12

2.5.1 反相器结构..............................................................................................................12

2.5.2 噪声容限..................................................................................................................12

2.5.3 转换时间、传播延时..............................................................................................13

第三章数字集成电路 ....................................................................................................................14

3.1 同步电路、异步电路 ........................................................................................................14

3.2 复位电路 ............................................................................................................................15

3.2.1 同步复位、异步复位..............................................................................................15

3.2.2 异步复位同步释放..................................................................................................15

3.3 D 触发器与 Latch ..............................................................................................................16

3.3.1 锁存器的危害..........................................................................................................16

3.4 FPGA ..................................................................................................................................17

3.5 门控时钟 ............................................................................................................................18

3.5.1 基于锁存器的门控时钟..........................................................................................18

3.5.2 基于触发器的门控时钟..........................................................................................18

3.6 CMOS 门的功耗..............................................................................................................19

3.6.1 动态功耗..................................................................................................................19

3.6.2 静态功耗..................................................................................................................19

3.7 低功耗设计 ........................................................................................................................20

3.7.1 系统级......................................................................................................................20

3.7.2 体系结构级..............................................................................................................20

3.7.3 RTL 级 .....................................................................................................................20

3.7.4 晶体管级..................................................................................................................20

3.8 独热码（one hot） ............................................................................................................20

第四章静态时序分析 ....................................................................................................................22

4.1 STA 内容............................................................................................................................22

STA 优缺点 .......................................................................................................................22

4.2 建立、保持时间 ................................................................................................................22

4.2.1 时钟周期约束..........................................................................................................22

4.2.2 保持时间约束..........................................................................................................23

4.3 时钟约束修复 ....................................................................................................................23

4.3.1 Tsetup 建立时间不满足，采用措施......................................................................23

4.3.2 Thold 保持时间修复 ...............................................................................................23

4.4 恢复、去除时间 ................................................................................................................24

4.5 时钟偏差、时钟抖动 ........................................................................................................24

4.6 如何时序收敛 ....................................................................................................................24

4.7 Fanout 优化 ........................................................................................................................25

4.8 亚稳态 ................................................................................................................................25

4.9 静态时序分析 ....................................................................................................................26

4.10 DC 流程..............................................................................................................................26

4.10.1 指定工艺库............................................................................................................26

4.10.2 读入设计文件........................................................................................................26

4.10.3 设定设计的约束条件............................................................................................26

4.10.4 输出报告................................................................................................................28

4.10.5 保存数据................................................................................................................28

4.10.6 脚本案例................................................................................................................28

4.11 输入输出延时.................................................................................................................29

4.11.1 定义........................................................................................................................29

4.12 跨时钟域的 STA ............................................................................................................30

4.12.1 域内........................................................................................................................30

4.12.2 域间........................................................................................................................30

第五章跨时钟域传输 ....................................................................................................................31

5.1 单 bit 信号跨时钟域传输 ..................................................................................................31

5.1.1 电平信号传输..........................................................................................................31

5.1.2 边沿检测同步器（慢到快）..................................................................................31

5.1.3 脉冲信号传输（快到慢）......................................................................................32

5.1.4 结绳法......................................................................................................................33

5.2 多 bit 信号跨时钟域传输 ..................................................................................................33

5.2.1 格雷码......................................................................................................................33

5.2.2 握手协议..................................................................................................................33

5.2.3 异步 FIFO................................................................................................................34

5.2.4 异步双口 RAM .......................................................................................................34

5.3 同步 FIFO...........................................................................................................................34

5.4 异步 FIFO...........................................................................................................................35

5.4.1 读写指针表示..........................................................................................................35

5.4.2 读空、写满判断......................................................................................................35

5.4.3 指针同步延迟的影响..............................................................................................36

5.4.4 FIFO 深度 ................................................................................................................37

第六章片上系统 ............................................................................................................................38

6.1 流水线设计 ........................................................................................................................38

6.2 Cache ..................................................................................................................................38

6.2.1 Cache 一致性问题：...............................................................................................38

6.3 多处理机 Cache 一致性问题 ............................................................................................39

6.3.1 监听协议..................................................................................................................39

6.3.2 目录协议..................................................................................................................39

6.3.3 Cacheline..................................................................................................................39

6.3.4 MESI ........................................................................................................................40

6.4 DMA...................................................................................................................................40

6.5 SDRAM ..............................................................................................................................40

6.6 FLASH................................................................................................................................40

6.7 I2C ....................................................................................................................................41

6.8 SPI.......................................................................................................................................41

第七章 Verilog ................................................................................................................................43

7.1 逻辑值 ................................................................................................................................43

7.2 ~ 按位取反 ........................................................................................................................43

7.3 Task 和 function .................................................................................................................43

7.4 无损定点化 ........................................................................................................................45

第八章 RTL 代码............................................................................................................................46

8.1 序列检测器 ........................................................................................................................46

8.2 偶数分频器 ........................................................................................................................47

8.2.1 二分频电路..............................................................................................................47

8.2.2 任意偶分频..............................................................................................................47

8.3 奇数分频器 ........................................................................................................................48

8.4 PWM...................................................................................................................................50

8.5 脉冲展宽 ............................................................................................................................51

8.6 按键消抖 ..........................................................................................................................52

8.7 无毛刺切换时钟 ..............................................................................................................53

8.8 串并转换 ..........................................................................................................................53

8.9 异步双口 RAM ..................................................................................................................55

第九章附录笔试题 ......................................................................................................................56

9.1.1 相关笔试题..............................................................................................................56

9.2 串行总线 ............................................................................................................................57

9.3 环形振荡器 ........................................................................................................................58

9.4 两个噪声源叠加后的均方根噪声幅度 ............................................................................58

9.5 傅里叶变换 ........................................................................................................................58

9.6 DFT 可测性设计................................................................................................................58

9.7 互调串扰耦合 ....................................................................................................................59

9.8 线与逻辑 ............................................................................................................................59

9.9 取对数函数 ........................................................................................................................59

9.10 取绝对值.........................................................................................................................60

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